• Sr. Principal ASIC/Analog Design Engineer

    Teledyne (Goleta, CA)
    …team in analysis techniques to confirm architectural approach meets customer needs + Design and analyze block level circuitry to support architectural approach ... and analysis techniques + Experience with infrared image sensor design and associated detectors + Architectural level ...sensor design and associated detectors + Architectural level CMOS analysis including noise and power + Leadership… more
    Teledyne (07/03/25)
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  • Silicon Engineer, Digital Design , Quantum…

    Google (Mountain View, CA)
    …microarchitectures and deliver high-quality documentation and artifacts to empower colleagues to design or use these blocks. + Implement block- level and chip- ... field. + 5 years of experience with digital logic design principles and RTL design concepts. +...+ benefits. Our salary ranges are determined by role, level , and location. Within the range, individual pay is… more
    Google (08/08/25)
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  • Senior ASIC Design Engineer

    NVIDIA (Santa Clara, CA)
    …them in complex GPU and Tegra chips. The team is also handling the architecture, design , and synthesis of multiple System- level modules. What you'll be doing: + ... + Collaborate with architects, ASIC designers, and verification engineers to design sophisticated system- level modules such as Floorsweep, In-silicon… more
    NVIDIA (06/19/25)
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  • Principal or Senior Principal Design

    Northrop Grumman (Redondo Beach, CA)
    Design Software Engineer (** **Logging/Telemetry/Data handling)** **What You'll Get to Do:** IPT- Level role, member of SW Design Team. This role - a software ... large amounts of data - works at the Segment/IPT level of an extremely complex System comprised of multiple...and emerging technologies. This engineer will support the software design team lead and partner with other engineering functions… more
    Northrop Grumman (08/31/25)
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  • Systems Engineer, Power Design SME

    Celestica (San Jose, CA)
    …mechanical and thermal engineers. You will drive system architecture of multi-tiered power network design from rack level power distribution down to the board ... Experience with high power, low noise, efficient, high density board level power design , including relevant simulations, analysis , test vehicles, and test plans… more
    Celestica (08/30/25)
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  • Principal / Senior Principal Controls Software…

    Northrop Grumman (Redondo Beach, CA)
    …is seeking **Principal / Senior Principal Controls Software Design Engineer.** **What** **You'll** **Get to Do:** IPT- Level ... Design Team. This role - a software design engineer focusing on Controls Software - works at...focusing on Controls Software - works at the Segment/IPT level of an extremely complex System comprised of multiple… more
    Northrop Grumman (08/28/25)
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  • Electrical Engineer, Cable and Harness…

    General Atomics (San Diego, CA)
    …for high-reliability aerospace and satellite applications. + Actively participate in system- level design across all project phases, through subsystem ... drive, talent, and experience in Aerospace Cable and Harness design who also thrives in a fast-paced, Research and...Siemens Capital E/E Architecture tools, Siemens NX CAD, other system- level harnessing tools (Zuken, etc), MS Visio (or similar)… more
    General Atomics (08/03/25)
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  • SOC RTL Design Engineer, Hardware Compute…

    Amazon (Sunnyvale, CA)
    … and implementation of large complex SoCs. Develop chip level and subsystem level netlists integrating IPs and new design . - Work with Chip Architects to ... with early RTL power analysis - Experience with gate level testing and multi clock design practices - Successful tape outs of complex, high-volume SoCs… more
    Amazon (07/24/25)
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  • FPGA/ASIC Design Engineer (Silicon…

    SpaceX (Irvine, CA)
    …+ Optimize designs for power, performance and area + Participate in the design process starting with high- level conceptual and architectural discussions and ... hours and weekends as needed COMPENSATION & BENEFITS: Pay range: ASIC/FPGA Design Engineer/ Level I: $120,000.00 - $145,000.00/per year ASIC/FPGA Design more
    SpaceX (06/12/25)
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  • Structures Design Engineer (Falcon…

    SpaceX (Hawthorne, CA)
    …various SpaceX sites (up to 25%) COMPENSATION AND BENEFITS: Pay range: Structures Design Engineer/ Level I: $95,000.00 - $115,000.00/per year Structures Design ... Structures Design Engineer (Falcon & Dragon) Hawthorne, CA Apply...Level II: $110,000.00 - $130,000.00/per year Your actual level and base salary will be determined on a… more
    SpaceX (09/02/25)
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