- NVIDIA (Santa Clara, CA)
- …needle! As a member of our Mixed Signal team, you will lead the design of CMOS high-speed interface circuits and mixed-signal circuits. Strong hands-on experience in ... and bring up. What you'll be doing: + Lead design and implementation of high speed interface circuit +...of lab instrumentation is required + Knowledge in system level timing budget, signal integrity, and power integrity is… more
- SpaceX (Sunnyvale, CA)
- …extended hours and weekends as needed COMPENSATION AND BENEFITS: Pay range: Design Verification Engineer/ Level I: $130,000.00 - $155,000.00/per year Design ... Design Verification Engineer (Silicon Engineering) Sunnyvale, CA Apply...Responsible for digital ASIC verification at block and system level + Write and review test plans, develop test… more
- Insight Global (Milpitas, CA)
- …level applications. This is a hands-on technical role requiring strong circuit- level design experience and full IC tapeout ownership. Key Responsibilities: ... circuits meeting stringent signal integrity and jitter performance targets Own block- level schematic design and verification in Cadence or Synopsys… more
- Northrop Grumman (Palmdale, CA)
- …history. Northrop Grumman Aeronautics Systems has an opening for a **Structural Design Engineer** to join our team of qualified diverse individuals. The position ... - 10 hours/day schedule.** . **Roles and responsibilities:** + Develop " Design for Producibility" solutions to difficult problems that are thorough, imaginative,… more
- General Motors (Mountain View, CA)
- …hardware/software integration and product development lifecycle + Familiarity with board- level hardware design , mechanical engineering, and validation processes ... **Job Description** **Staff Technical Program Manager, In-House Hardware Design and Development** **Hybrid:** This role is categorized as Hybrid, and the successful… more
- Meta (Sacramento, CA)
- **Summary:** Meta is seeking a Connectivity Engineer to join the Design Engineering and Construction (DEC) team. Our data centers are the foundation upon which our ... stored on Meta 's server banks.The DEC Connectivity Engineer will provide site level support to ensure DEC telecommunication projects are being executed on schedule,… more
- Google (Sunnyvale, CA)
- ASIC Design Verification Engineer, University Graduate _corporate_fare_ Google _place_ Sunnyvale, CA, USA **Early** Experience completing work as directed, and ... using SystemVerilog for ASICs. + Experience in power aware verification, gate level simulations, and post silicon bring-up. + Experience with the full verification… more
- Palo Alto Networks (Santa Clara, CA)
- …bash or tcsh). + Demonstrated strength in: + Defining micro-architecture from high- level requirements. + Datapath design expertise for intricate synch/asynch ... that powers our next-generation firewall platforms. You will own module design from specification through silicon bring-up, working with world-class verification and… more
- Applied Materials (Santa Clara, CA)
- …DDR and high-speed IO. * Good knowledge of digital electronics, schematics, and board- level design . * Strong debugging skills using ChipScope and lab equipment. ... produce virtually every new chip and advanced display in the world. We design , build and service cutting-edge equipment that helps our customers manufacture display… more
- Northrop Grumman (Redondo Beach, CA)
- …(NGMC) (https://www.northropgrumman.com/what-we-do/mission-solutions/microelectronics) is seeking **IPT Software Design Manager 3.** **What** **You'll** **Get to ... Do:** This role works at the Segment/IPT level of an extremely complex System comprised of multiple...and emerging technologies. This engineer will lead the software design team and partner with other engineering function leaders… more