• Senior ASIC Design Engineer

    NVIDIA (Santa Clara, CA)
    …skills and ability to collaborate with multiple teams. + Experience in RTL design (Verilog), verification and logic synthesis. + Strong coding skills in ... The clocks group is looking for a top-notch ASIC engineer to join the team. The Team is responsible...and CPU clocking. The team collaborates with the front design team to understand the clocking requirements for the… more
    NVIDIA (07/29/25)
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  • IC Design Engineer

    Broadcom (San Jose, CA)
    …Account, please Sign-In before you apply.** **Job Description:** **Job Description: IC Design Engineer ** + Participate in IP level architectural definition ... years of relevant industry experience. Advanced degree preferred Must have strong Logic Design , RTL coding (Verilog HDL) and debugging skills Must have an… more
    Broadcom (07/03/25)
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  • Senior Design For Test Engineer

    Microsoft Corporation (Santa Clara, CA)
    …to CPU-based alternatives Microsoft DPU team in Santa Clara is looking for a Senior Design For Test Engineer to help develop their next generation complex SoCs ... including shared bus MBIST architecture + EDT, SSN, and logic bist insertion and validation + ATPG pattern generation...experience. + 2+ years of industry experience as a Design For Test (DFT) engineer . + Hands… more
    Microsoft Corporation (07/31/25)
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  • Sr. RTL Design Engineer - Wireless…

    Amazon (San Diego, CA)
    …underserved communities around the world. Come work at Amazon! We're hiring a Sr. RTL Design Engineer - Wireless Modem within a high performance ASIC design ... Able to interpret reference models in MATLAB. - Involve in control plane logic design and interfaces to bus fabrics. - Explore and propose innovative ideas and… more
    Amazon (06/28/25)
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  • FPGA Design Engineer

    Tarana Wireless (Milpitas, CA)
    …You'll Need: + BS in Electrical Engineering (MS preferred) + 2+ years of FPGA logic design experience + Expertise in high-speed digital design + Hands-on ... the foundation of tomorrow's wireless infrastructure. What You'll Do: + Design , implement, and debug logic for large FPGAs + Simulate, test, and validate … more
    Tarana Wireless (06/18/25)
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  • Senior ASIC Physical Design and Timing…

    NVIDIA (Santa Clara, CA)
    …human inventiveness and intelligence. We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. If you want to challenge yourself ... paths through ECOs including crosstalk and noise analysis. + Expertise in physical design and optimization eg, placement, routing, cell sizing, buffering, logic more
    NVIDIA (06/30/25)
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  • Senior Design for Debug Architect…

    NVIDIA (Santa Clara, CA)
    …looking for a Senior Design for Debug (DFD) Architect and Methodology Engineer ! NVIDIA is seeking a DFD Architect to implement hardware and software solutions to ... synchronization & bus protocols, interconnect networks and/or caches. + Expertise in design for debug techniques and methodologies, integrated logic analyzers… more
    NVIDIA (06/11/25)
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  • SOC Physical Design Engineer

    Amazon (Sunnyvale, CA)
    …at edge. Work hard. Have fun. Make history. As a Physical Design Engineer , you will: - Work with RTL/ logic designers to drive architectural feasibility ... is powering the latest generation of Echo devices is looking for a Sr. Physical Design Engineer to continue to innovate on behalf of our customers. We are a part… more
    Amazon (07/27/25)
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  • Principal FPGA / Rtl Design Engineer

    Silvus Technologies (Irvine, CA)
    …fulfilling career. THE OPPORTUNITY Silvus is seeking a full-time Principal FPGA / RTL Design Engineer who will report to the Senior Engineering Director for ... challenging real-world communication needs. The Principal FPGA / RTL Design Engineer position will be based at...timing closure. * Hardware verification and troubleshooting; familiarity with logic analyzers. * Provide support to the RF and… more
    Silvus Technologies (07/04/25)
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  • E/E & Semiconductor Engineer - Electrical…

    Capgemini (Santa Clara, CA)
    …_Programmer/Analyst_ **Organization:** _ERD PPL US_ **Title:** _E/E & Semiconductor Engineer - Electrical Design Validation engineer_ **Location:** _CA-Santa ... delivery, thermal, and mechanical requirements + Work closely with in-house board design teams and external contractors to guide and review schematic, layout,… more
    Capgemini (06/28/25)
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