• Senior ASIC Design Engineer

    NVIDIA (Santa Clara, CA)
    We are now looking for a Senior ASIC Design Engineer . NVIDIA is seeking ASIC Design Engineers to implement the world's leading SoC's and GPU's. This position ... + Great understanding of ASIC design flow including RTL design , verification, logic synthesis and timing analysis. + Exposure to Digital systems and VLSI… more
    NVIDIA (09/09/25)
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  • Senior ASIC Design Engineer

    NVIDIA (Santa Clara, CA)
    We are now looking for a motivated Senior ASIC Design Engineer to join our dynamic and growing team in our Circuit Solutions Group! NVIDIA has continuously ... experience) + 6+ years of proven experience and a background in logic design , Verilog and/or System-Verilog with a deep understanding of physical design more
    NVIDIA (08/27/25)
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  • Senior RTL Design Engineer , Low…

    Google (Sunnyvale, CA)
    Senior RTL Design Engineer , Low Power, ML Accelerators...equivalent practical experience. + 5 years of experience in logic design , digital ASIC, or SoC ... design . + Experience with RTL (Register Transfer Level) design using Verilog or SystemVerilog. + Experience with low-power design or power reduction… more
    Google (11/20/25)
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  • Intern - Design Engineer

    Micron Technology, Inc. (San Jose, CA)
    …technology development, design , and system-level optimization. **Position Overview** As a ** Design Engineer ** , you will develop and analyze digital and ... ensure manufacturability, cost efficiency, quality, and time-to-market. **Responsibilities** + Design , layout, and optimize Memory/ Logic /Analog circuits for new… more
    Micron Technology, Inc. (11/19/25)
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  • Senior Principal Emulation Design

    Cadence Design Systems, Inc. (San Jose, CA)
    …make an impact on the world of technology. We are seeking a highly skilled Design Engineer to join our Palladium Solutions Development team, to drive the ... components in emulation platforms. Key Responsibilities: + Lead the design and deployment of PHY logic models...Lead the design and deployment of PHY logic models for emulation platforms including Palladium and Protium.… more
    Cadence Design Systems, Inc. (11/18/25)
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  • DSP or Serdes RTL Sr Principal Digital…

    Cadence Design Systems, Inc. (San Jose, CA)
    …but is not limited to: + Digital microarchitecture definition and documentation + RTL logic design , debug and functional verification + Strong background in DSP ... and developing flows at all phases of the digital design and functional verification. It is further expected that...Substantial experience with Verilog is required, as are excellent logic and debug skills. Engineering expertise in mixed-signal IP… more
    Cadence Design Systems, Inc. (10/17/25)
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  • System Design Engineer

    NVIDIA (Santa Clara, CA)
    …life's work, to amplify human creativity and intelligence. We are now looking for a System Design Engineer in the System Product Team. In this role, you will be ... working with peer system design engineers to develop NVIDIA GPU/Tegra based products for...with using lab tools such as oscilloscopes, multimeters, and logic analyzers. + Comfortable working in various Linux environments… more
    NVIDIA (11/18/25)
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  • FPGA Digital Design Engineer 3/4

    Northrop Grumman (Los Angeles, CA)
    …making history. Northrop Grumman Advanced Weapons has an opening for a FPGA Digital Design Engineer with an active clearance, to join our team of qualified, ... circuitry for digital electronic equipment and other hardware systems. Determines design approaches and parameters. Analyzes equipment to establish operating data,… more
    Northrop Grumman (09/27/25)
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  • RTL Design Engineer , Multimedia…

    Google (Mountain View, CA)
    RTL Design Engineer , Multimedia and Machine Learning Accelerators _corporate_fare_ Google _place_ Mountain View, CA, USA **Mid** Experience driving progress, ... practical experience. + 8 years of experience designing RTL digital logic using SystemVerilog for FPGA/Application-Specific Integrated Circuits (ASICs) or equivalent… more
    Google (11/20/25)
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  • Senior FPGA Design Engineer

    Google (Goleta, CA)
    Senior FPGA Design Engineer , Quantum AI _corporate_fare_ Google _place_ Goleta, CA, USA **Mid** Experience driving progress, solving problems, and mentoring more ... practical experience. + 4 years of experience in Field Programmable Gate Array (FPGA) design and development. + 4 years of experience with RTL design using… more
    Google (11/07/25)
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