• Digital Design Engineer

    BrainChip, Inc. (Laguna Hills, CA)
    BrainChip is seeking a Digital Design Engineer to join a team working on cutting-edge and novel AI hardware. The primary job function is to work with team ... be part of our Hardware Development group. The Digital Design Engineer needs to be able to...or certification required 3+ years of experience in digital logic design Good understanding of modern computational… more
    BrainChip, Inc. (03/13/25)
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  • IC Design Engineer

    Broadcom (San Jose, CA)
    …Description:** Broadcom Inc. is looking for a creative and self motivated Digital IC Design Engineer to join the Data Center Solutions Group . This position ... the RTL code and the verification environment to reflect functionality. * Design of logic relating to the NVMe and PCIe specifications, as well as general… more
    Broadcom (04/08/25)
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  • Senior ASIC Design Engineer

    NVIDIA (Santa Clara, CA)
    We are now looking for a Senior ASIC Design Engineer . NVIDIA is seeking ASIC Design Engineers to implement the world's leading SoC's and GPU's. This position ... + Great understanding of ASIC design flow including RTL design , verification, logic synthesis and timing analysis. + Exposure to Digital systems and VLSI… more
    NVIDIA (03/12/25)
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  • DSP or Serdes RTL Lead Digital Design

    Cadence Design Systems, Inc. (San Jose, CA)
    …but is not limited to: + Digital microarchitecture definition and documentation + RTL logic design , debug and functional verification + Strong background in DSP ... and developing flows at all phases of the digital design and functional verification. It is further expected that...Substantial experience with Verilog is required, as are excellent logic and debug skills. Engineering expertise in mixed-signal IP… more
    Cadence Design Systems, Inc. (05/08/25)
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  • Physical Design Engineer , TPU

    Google (Sunnyvale, CA)
    …related field, or equivalent practical experience. + 7 years of physical design experience with industry-standard tools, languages, and methodologies relevant to the ... development of silicon-based ICs and chips. + Experience in logic synthesis, PnR, timing closure, and static timing analysis. Preferred qualifications: + Master's… more
    Google (04/02/25)
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  • R&D Engineer IC Design

    Broadcom (San Jose, CA)
    …a Candidate Account, please Sign-In before you apply.** **Job Description:** ASIC/Layout Design Engineer : Oversees definition, design , verification, and ... documentation for ASIC development. Determines architecture design , logic design , and system simulation. Defines module interfaces/formats for simulation.… more
    Broadcom (04/15/25)
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  • Senior Mixed Signal Design Engineer

    NVIDIA (Santa Clara, CA)
    We are now hiring for a Senior Mixed-signal Design Engineer ! NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked ... USB) preferred + Have a deep understanding of Verilog or SystemVerilog, logic design and circuit modeling for mixed-signal blocks + Deep understanding of… more
    NVIDIA (04/13/25)
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  • Senior Mixed Signal Design Validation…

    NVIDIA (Santa Clara, CA)
    …the boundaries of what's possible. We are looking for an experienced Mixed Signal Design Validation Engineer with a strong background in LPDDR, GDDR, and HBM ... Mixed signal design , PISI team, hardware, firmware, and Memory qualification engineer , to resolve issues and improve the performance for memory interfaces. +… more
    NVIDIA (04/11/25)
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  • ASIC Design Engineer , Platform IP,…

    Google (Mountain View, CA)
    …a related field, or equivalent practical experience. + 3 years of experience with digital logic design principles, RTL design concepts, and languages such as ... Verilog or SystemVerilog. + Experience with logic synthesis techniques to improve RTL code, performance and...RTL code, performance and power as well as low-power design techniques. + Experience with ARM-based SoCs, interconnects and… more
    Google (04/10/25)
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  • Senior Principal Design Engineer

    Cadence Design Systems, Inc. (San Jose, CA)
    …customers, our communities, and each other-every day. Key Responsibilities The Senior Principal Design Engineer will define the DFT Architecture for the next ... verification including Scan, PMBIST, JTAG and other DFT's related logic . Additionally, they will define and develop methodology for...At least 8 years of relevant hands-on experience in Design for Test (DFT). + Clear understanding of key… more
    Cadence Design Systems, Inc. (04/17/25)
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