• Hardware Engineer, Quantum Superconducting Digital…

    Google (Goleta, CA)
    …digital circuit design. + 1 year of experience with one or more superconductor logic family (eg, RSFQ, ERSFQ, RQL, HFQ, AQFP, and other related families). ** ... Preferred qualifications:** + Master's or PhD degree in Electrical...experience in the design and simulation of superconductor digital logic circuits. + Experience with superconducting qubits. + Experience… more
    Google (11/27/25)
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  • Advanced Device Modeling Expert - TCAD

    Applied Materials (Santa Clara, CA)
    …to drive new innovations that enable a wide range of advanced Logic -Memory devices and technologies, and associated material and processes interactions. You can ... unit process and integration flow development for next generation logic and DRAM nodes. You will play a key...+ Passionate and highly motivated to learn new things ** Preferred Qualifications** + Experience with device and circuit level… more
    Applied Materials (10/21/25)
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  • IC Design Engineer

    Broadcom (Irvine, CA)
    …debug efforts **Job Requirements** BS+12 Years of relevant industry experience. Advanced degree preferred Must have strong Logic Design, RTL coding (Verilog HDL) ... techniques including UPF/CPF Must be familiar with design constraint generation, logic synthesis, timing closure analysis and Clock/Reset domain crossing checks Must… more
    Broadcom (11/18/25)
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  • Module Lab Electronics Technician

    Teledyne (Newark, CA)
    …validation of electronic circuit cards, FPGA-based systems, microcontrollers, and programmable logic devices. The ideal candidate will have hands-on experience with ... digital and analog electronics, and industrial control logic (eg, ladder logic ). **Key Responsibilities:** + Perform functional and parametric testing of… more
    Teledyne (12/02/25)
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  • DFT Engineer, Google Cloud

    Google (Sunnyvale, CA)
    …not limited to) ATE, MBIST, JTAG, or System Level Test (SLT). ** Preferred qualifications:** + Master's degree or PhD in Electrical Engineering, Computer Engineering, ... will also be responsible for design verification of test logic , test pattern generation and debugging and test coverage...share more about the specific salary range for your preferred location during the hiring process. Please note that… more
    Google (12/13/25)
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  • Principal FPGA Electrical Engineer

    Oracle (Santa Clara, CA)
    …of responsibilities (but not limited to) may include:_ + _Architect and partition FPGA logic ._ + _Design and Code logic needed for next generation cloud compute ... Ascent Lint._ + _Experience with I2C/SPI/eSPI/PMBUS/SVID/SGPIO/etc communication bus is preferred ._ + _Strong knowledge and application of high-speed design… more
    Oracle (11/25/25)
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  • Senior Technical Lead, Hardware Engineering…

    Cisco (Milpitas, CA)
    …with electrical diagnostics and measurement equipment - oscilloscopes, digital multimeter, Logic Analyzers, Signal or Traffic generators etc. ** Preferred ... Qualifications** *Experience with CPUs/embedded CPUs, FPGAs/PLDs and good understanding of control interfaces such as PCIe, MDIO, SPI, I2C *Experience with MS Excel and data collection / analysis *Familiarity with Python, PERL or similar scripting and… more
    Cisco (11/12/25)
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  • SoC DFT Engineer, Google Cloud

    Google (Sunnyvale, CA)
    …not limited to) ATE, MBIST, JTAG, or System Level Test (SLT). ** Preferred qualifications:** + Master's degree or PhD in Electrical Engineering, Computer Engineering ... you will also be responsible for diagnosing memory and logic failures, increasing production quality, and enhancing yield and...share more about the specific salary range for your preferred location during the hiring process. Please note that… more
    Google (11/25/25)
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  • Product Engineering Intern - Genus Synthesis…

    Cadence Design Systems, Inc. (San Jose, CA)
    …Collaborate with the Product Engineering team to evaluate and improve Genus, a logic synthesis tool used to optimize Power, Performance, and Area (PPA) for advanced ... challenges in physically aware synthesis, bridging the gap between logic synthesis and place & route. + Support internal...for new features based on internal and external feedback. Preferred Qualifications + Currently pursuing an MS in Electrical… more
    Cadence Design Systems, Inc. (10/29/25)
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  • Senior Silicon Bringup and Test Lead, Raxium

    Google (Fremont, CA)
    …Electronic Design Automation (EDA) tools for circuit design and analysis. ** Preferred qualifications:** + 15 years of experience in Application-Specific Integrated ... Chip (ASIC/SoC) design, with a focus on both digital logic design and Design for Testability (DFT) implementation. +...share more about the specific salary range for your preferred location during the hiring process. Please note that… more
    Google (11/22/25)
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