• Senior Physical Design Methodology…

    NVIDIA (Santa Clara, CA)
    … Engineering + Proven track record of PPA improvement on high performance and low power designs in advanced technology nodes + Strong understanding of physical ... files such as UPF, and use of FSDB/SAIFs for power optimization + Understanding of hierarchical design , pinning and budgeting flows + Experience with power more
    NVIDIA (11/19/25)
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  • Sr. ASIC Design Engineer

    Amazon (Hawthorne, CA)
    …-Experience with products that have gone to volume production -Hands on experience in low power design techniques -Strong written and verbal skills Preferred ... The team works backwards from customer requirements to build super- low power , energy efficient designs that include..., performance, and area for significant IPs early in design cycle -Execute on design specifications to… more
    Amazon (01/06/26)
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  • Senior SRAM Engineer , Circuit…

    NVIDIA (Santa Clara, CA)
    …RAM implementations for NVIDIAs wide array of processing chips. Be it high speed, low power , multiport, we engage closely with processor architecture teams to ... We are now looking for a Senior SRAM Engineer ! The Full Custom Macro team at NVIDIA...power these chips. What you'll be doing: + Design best-in-class SRAM circuits using state-of-the-art technology processes +… more
    NVIDIA (01/02/26)
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  • Senior SRAM Circuit Design Engineer

    NVIDIA (Santa Clara, CA)
    …members on the new process design challenges, have the chance to create novel low power and high performance circuits, and develop in-house design and ... level circuit design , modeling and performance analysis process and optimize design for power , timing, area and yield + You'll make the layout floorplan and… more
    NVIDIA (11/20/25)
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  • IC Design Engineer

    Broadcom (San Jose, CA)
    …Experience working with advanced semiconductor technologies. Experience in implementing low power and high-performance cores Excellent communication and ... Team is responsible for standard cell development and custom design solutions that power cutting-edge AI compute...engineer to join our team. Job Description: Layout design of digital high-performance blocks Timing closure of the… more
    Broadcom (11/06/25)
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  • R&D IC Design Engineer

    Broadcom (Irvine, CA)
    …as hands-on lab debugging experiences Good knowledge of RTL simulation and synthesis. In-depth knowledge for design for low power and design for test and ... & test plans for design validation Perform design tradeoff analysis - leakage, dynamic power , die size, schedule, resource, priority, etc. silicon bring up… more
    Broadcom (12/30/25)
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  • R&D IC Design Engineer

    Broadcom (Irvine, CA)
    …lab debugging experiences + Good knowledge of RTL simulation and synthesis. + In-depth knowledge for design for low power and design for test and ... & test plans for design validation + Perform design tradeoff analysis - leakage, dynamic power , die size, schedule, resource, priority, etc. + silicon bring… more
    Broadcom (12/30/25)
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  • Sr. Hardware Development Engineer , AWS…

    Amazon (Cupertino, CA)
    Description What you will do: As a member of the AWS Board Core Design & Services team you will own next-generation server components. You will have demonstrated ... will interact with an interdisciplinary team of engineers to design , develop, validate, and launch at large scale. You'll...in data centers and platform. We cover everything from low level hardware to embedded software and systems that… more
    Amazon (10/31/25)
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  • Senior ASIC Physical Design Engineer

    NVIDIA (Santa Clara, CA)
    …human inventiveness and intelligence. What you'll be doing: + You will drive physical design of high-frequency and low - power CPUs, GPUs, SoCs at block ... and intelligence. We are now looking for a motivated Senior ASIC Physical Design Engineer , Netlisting to join our dynamic and growing team. If you want to… more
    NVIDIA (01/08/26)
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  • Sr Principal Design Engineer

    Cadence Design Systems, Inc. (San Jose, CA)
    …testing + Proficiency in Verilog/SystemVerilog and its simulation environment + Good knowledge of IC design for high-speed and low power + At least five ... Specific duties include: + Be responsible for high-performance memory IP architecture design , owning the IC micro-architecture, timing budget, power analysis… more
    Cadence Design Systems, Inc. (12/10/25)
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