- Amazon (Cupertino, CA)
- …Integration and design of silicon and 2.5D packaging -Support the physical design team, review clocking and timing constraints -Drive cross-functional triage ... an HBM/DDRx Phy expert with role in the definition, design and validation of AWS next generation ML Chips,...the outstanding and meaningful opportunity to participate in the design and execution of all HBM, Memories and Serdes… more
- Amazon (Cupertino, CA)
- …Integration and design of silicon and 2.5D packaging - Support the physical design team, review clocking and timing constraints - Drive cross-functional ... an HBM/DDRx Phy expert with role in the definition, design and validation of AWS next generation ML Chips,...the outstanding and meaningful opportunity to participate in the design and execution of all HBM, Memories and Serdes… more
- Amazon (Sunnyvale, CA)
- …optimization, multi-project wafer runs, and strategic volume commitments - Partner with silicon design , verification, and physical design teams to influence ... background in silicon development, including understanding of advanced process nodes, physical design , DFM, and advanced packaging technologies - Demonstrated… more
- Actalent (Irvine, CA)
- …+ Advanced experience with AutoDesk Inventor or AutoCAD Electric + Advanced experience with physical or P&C substation design (AIS and/or GIS) + Substation ... advanced experience with AutoCAD Electric or AutoDesk Inventor (SDS) and physical substation design (AIS and/or GIS). The role may require collaboration with… more
- NVIDIA (Santa Clara, CA)
- … Design Engineers, Low Power Engineers, Performance Engineers, Software Engineers, and Physical Design teams to study and implement energy modeling techniques ... and artificial intelligence workloads, and will allow us to influence architectural, design , and power management improvements. What you'll be doing: + Work with… more
- NVIDIA (Santa Clara, CA)
- …you will own RTL synthesis and gate level optimization tasks + Collaboration with physical design to address timing, area, congestion tradeoffs + Drive timing ... as part of the advanced technology team to optimize design tradeoffs and methodology on next generation CMOS technology....closure and power/area optimization across multiple design blocks + Work with DFT and Verification teams… more
- Arrow Electronics (San Jose, CA)
- …a member of design team who oversees **fullchip SDCs** and works with physical design and DFT teams to close **fullchip timing** in multiple timing modes. ... + Option to also do block level RTL design or block or top-level IP integration. + Helping...and quality of SDCs as early as possible in design cycle. + Reviewing block level SDCs and clocking… more
- Stantec (Los Angeles, CA)
- …join our Physical Security and Technology Practice with specific experience in Physical Security consulting and design . The Physical Security Consultant ... detection, duress alarms, perimeter protection, infant protection and other physical security systems design - Knowledge of IT and OT networks - Knowledge… more
- Google (Mountain View, CA)
- …teams for high quality tape-outs. + Experience in working with verification, DFT, physical design and emulation teams. + Experience in supporting the Post ... will bring a breadth of ideas across silicon Architecture, RTL, Design Verification (DV), and Physical Design (PD) and silicon productization. You will be… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …Innovus product. Innovus is a complete digital implementation product that encompasses physical design and logic synthesis. The product breadth means we ... debugging and supporting the Innovus product. This specific role will require physical design and synthesis domain knowledge on how each engine and what roles… more