• Principal Software Engineer (Synthesis…

    Cadence Design Systems, Inc. (San Jose, CA)
    …algorithms, physical optimization is big plus Prior R&D experience working on EDA / IC physical design tools is a plus . Hands on experience using the above ... physical design tools for design closure and knowledge of physical design flows a plus. The annual salary range for California is $136,500 to… more
    Cadence Design Systems, Inc. (06/14/25)
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  • Principal Product Engineer

    Cadence Design Systems, Inc. (San Jose, CA)
    …Experience in design and EDA with an emphasis on Cadence tools of Synthesis, Physical Design & timing closure at 20nm or below nodes + Prior Designer, ... + Experience in Logic Design and Synthesis, Formal Verification, Low Power design , Physical Design and Timing Closure for block level and top level… more
    Cadence Design Systems, Inc. (06/10/25)
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  • EMIR Sign-off, Flow and Methodology Engineer,…

    Google (Sunnyvale, CA)
    …or equivalent practical experience. + 5 years of technical experience in physical design disciplines involving power delivery and advanced process technology ... full-chip level, including proactive floorplanning and defining standard cell usage with physical design owners. + Experience establishing EMIR budgets, defining… more
    Google (08/27/25)
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  • Principal Analog Engineer

    Microsoft Corporation (Mountain View, CA)
    …quality of incoming IPs and facilitate smooth integrations by working closely with Logic design and Physical design teams. + Interface with architecture, ... physical design (PD), design for test (DFT), and other teams to optimize tradeoffs within the design + Provide technical leadership through mentorship and… more
    Microsoft Corporation (08/14/25)
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  • Senior Synthesis Flow CAD Engineer

    NVIDIA (Santa Clara, CA)
    …of Python, Perl , Tcl, C/C++ + Knowledge or experience with logic synthesis, physical design , formal equivalence checking. + Proven track record developing flows ... software engineering methodologies + Build flows for methodologies incorporating logic/ physical synthesis, design planning, equivalence checking for… more
    NVIDIA (06/10/25)
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  • Lead Software Engineer, Innovus

    Cadence Design Systems, Inc. (San Jose, CA)
    …R&D engineer, who will be involved in developing a multi-threaded and distributed physical design core engine in Innovus Implementation System. The position ... working on IC physical designs toolsHands on experience using the above physical design tools for design closure and knowledge of physical more
    Cadence Design Systems, Inc. (07/25/25)
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  • ASIC Implementation Engineer - Static Verification

    Meta (Sunnyvale, CA)
    …Emulation Engineers in supporting them with the handoff tasks. Interact with Physical Design Engineers and provide them with timing/congestion feedback **Minimum ... SOC Design Integration and Front-End Implementation 18. Knowledge of Timing/ physical libraries, SRAM Memories 19. Experience with Netlist CDC Analysis and… more
    Meta (08/01/25)
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  • Technical Program Manager, ASIC

    Amazon (San Diego, CA)
    …as architecture, front end design , pre-silicon verification, FPGA prototyping, Emulation, Physical design , BROM, FW, substrate and package design , ... development from architecture definition, RTL design , Verification, IP design , Physical design , silicon bring up, test, characterization, quality,… more
    Amazon (08/27/25)
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  • Technology Program Manager, Commodity Management

    Google (Sunnyvale, CA)
    …Python, Perl, Tcl) for automation of design flows. + Understanding of physical design concepts (floor planning, place and route, clock tree synthesis). A ... closure to meet performance and power goals. + Integrate Design -for-Test (DFT) features, support physical design...goals. + Integrate Design -for-Test (DFT) features, support physical design for tape-out, and collaborate on… more
    Google (08/26/25)
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  • Senior DFx/RTL Engineer

    Cisco (San Jose, CA)
    …focus on Design -for-Test. You will work with Front-end RTL teams, backend physical design teams to understand chip architecture and drive DFT requirements ... + Your team will participate in the creation of Innovative Hardware DFT & physical design aspects for new silicon device models, bare die & stacked die, driving… more
    Cisco (07/22/25)
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