• Physical Design Flow and Methodology…

    Google (Sunnyvale, CA)
    Physical Design Flow and Methodology Engineer _corporate_fare_ Google _place_ Sunnyvale, CA, USA **Mid** Experience driving progress, solving problems, and ... workflows in a semiconductor environment. + Experience developing automated physical design workflows from RTL to GDS,...CAD flows such as place and route, EM/IR, static timing , etc. You will also possess a good command… more
    Google (09/28/25)
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  • Principal Physical Design…

    NVIDIA (Santa Clara, CA)
    …our diverse team today! The Advanced Technology Group is looking for a highly motivated Principal Physical Design Engineer to join our group. Do you have a ... proven EE background with an in-depth understanding of physical design , place and route, timing analysis, power analysis, IR drop analysis, process nodes and… more
    NVIDIA (07/31/25)
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  • Sr. Physical Design Engineer…

    Amazon (Cupertino, CA)
    …massive scale and rapid integration of emergent technologies. We're looking for an ASIC Physical Design Engineer to help us trail-blaze new technologies and ... designers to drive architectural feasibility studies, explore power-performance-area tradeoffs for physical design closure - Drive IO/Core block physical… more
    Amazon (10/02/25)
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  • Senior Physical Design Methodology…

    NVIDIA (Santa Clara, CA)
    …human inventiveness and intelligence. What you will be doing: + Developing innovative physical design methodologies for implementation of GPU, CPU and SOCs, with ... PPA (Power, Performance, Area) and runtime improvement of the physical design flow on advanced technology nodes...timing and RC correlation + Good understanding of design rules in advanced nodes and their impact on… more
    NVIDIA (08/20/25)
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  • Physical Design Methodology…

    NVIDIA (Santa Clara, CA)
    …human inventiveness and intelligence. What you will be doing: + Developing innovative physical design methodologies for implementation of GPU, CPU and SOCs, with ... PPA (Power, Performance, Area) and runtime improvement of the physical design flow on advanced technology nodes...methods and techniques + Strong background in STA, extraction, timing and RC correlation + Background with design… more
    NVIDIA (09/23/25)
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  • Physical Design Engineer V…

    Arrow Electronics (Santa Clara, CA)
    **Position:** Physical Design Engineer V...which includes, static timing analysis, IR/EM and physical verification through which design will be ... of memory, power planning, placement, clock building, routing + Design and development of sign off flows based on...validated based on the product specification + Design and development of Chip implementation flow, place and… more
    Arrow Electronics (10/01/25)
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  • Physical Design Engineer

    Broadcom (San Jose, CA)
    …before you apply.** **Job Description:** **Broadcom is looking for a senior level ASIC physical design engineer . In this highly visible role, you will ... or Computer Engineering with 6+ years of experience in Physical design .** + **Deep knowledge about industry...chip and block level.** + **Experience with CDC, static timing analysis methodologies and relevant tools.** + **Exposure to… more
    Broadcom (09/26/25)
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  • Principal Engineer , VLSI Design…

    SanDisk (Milpitas, CA)
    …of digital design in NAND Flash memory, focusing on micro architecture, RTL design , verification, logic synthesis, and timing analysis to deliver a design ... and verification in Verilog, RTL linting, clock domain crossing (CDC) analysis, design integration, synthesis, DFT, timing analysis and closure + Balance … more
    SanDisk (09/11/25)
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  • Staff Engineer , VLSI Design…

    SanDisk (Milpitas, CA)
    …of digital design in NAND Flash memory, focusing on micro architecture, RTL design , verification, logic synthesis, and timing analysis to deliver a design ... and verification in Verilog, RTL linting, clock domain crossing (CDC) analysis, design integration, synthesis, DFT, timing analysis and closure + Balance … more
    SanDisk (09/10/25)
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  • ASIC Physical Design Engineer…

    Amazon (Cupertino, CA)
    …you - come build the future with us! Key job responsibilities * Perform physical design for Amazon's machine learning custom silicon solutions * Participate in ... various aspects of physical design : full chip floorplanning, circuit analysis,...design : full chip floorplanning, circuit analysis, power/clock distribution, timing optimization, place and route, power integrity analysis, and… more
    Amazon (09/16/25)
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