• Senior ASIC Design Engineer

    NVIDIA (Santa Clara, CA)
    We are now looking for a motivated Senior ASIC Design Engineer to join our dynamic and growing team in our Circuit Solutions Group! NVIDIA has continuously ... , Verilog and/or System-Verilog with a deep understanding of physical design and VLSI + Experience with...of ASIC design flow including front end design and verification, DFT, and timing analysis… more
    NVIDIA (08/27/25)
    - Related Jobs
  • Senior Principal Digital Design

    Leonardo DRS, Inc. (Cypress, CA)
    …for surveillance and targeting applications. We are seeking a Senior Principal Digital Design Engineer to join the company in the development of strategic ... of 10 years of experience working in Electrical Engineering with emphasis in FPGA design + Ability to solve problems at circuit and system levels + Proven experience… more
    Leonardo DRS, Inc. (08/21/25)
    - Related Jobs
  • DSP or Serdes RTL Sr Principal Digital…

    Cadence Design Systems, Inc. (San Jose, CA)
    …static timing analysis and constraint development + Understanding of fundamental physical design flows and stages + Understanding impacts of analog and ... and developing flows at all phases of the digital design and functional verification. It is further expected that...well as a thorough understanding of the end-to-end digital design flow in order to accurately and efficiently collaborate… more
    Cadence Design Systems, Inc. (07/18/25)
    - Related Jobs
  • FPGA Digital Design Engineer 3/4

    Northrop Grumman (Los Angeles, CA)
    …making history. Northrop Grumman Advanced Weapons has an opening for a FPGA Digital Design Engineer with an active clearance, to join our team of qualified, ... Qualifications: . Experience with DSP, MATLAB, and SimuLink . Knowledgeable in FPGA physical constraints and achieving timing closure. . Experience with board or… more
    Northrop Grumman (09/27/25)
    - Related Jobs
  • IC Design Engineer

    Broadcom (Irvine, CA)
    …and technically strong engineer to join our team. Job Description: Layout design of digital high-performance blocks Timing closure of the blocks with best ... The Central Engineering Team is responsible for standard cell development and custom design solutions that power cutting-edge AI compute cores and CPUs. We are… more
    Broadcom (08/08/25)
    - Related Jobs
  • Staff Logic Circuit Design Engineer

    Micron Technology, Inc. (Folsom, CA)
    …digital design and RTL development + Good understanding on timing /area/power/complexity tradeoffs in designs + Experience with Synthesis & Constraints + ... HBM RTL designer will need to have significant experience front end digital design ! The designer will be responsible for the development several blocks. Development… more
    Micron Technology, Inc. (08/22/25)
    - Related Jobs
  • Design and Analysis Engineer

    The Boeing Company (Long Beach, CA)
    …Avionics & Flight Controls (AVFC) team is seeking a mid-career (Level 3) **Electrical Engineer ** to perform Design , Integration and Test activities in support of ... hardware-software integration and troubleshooting - Ability to diagnose data flow, timing issues, and interface mismatches using tools like protocol analyzers, logs,… more
    The Boeing Company (10/08/25)
    - Related Jobs
  • Principal design engineer , VLSI…

    SanDisk (Milpitas, CA)
    …and full chip circuit simulations to meet all performance specifications. + RTL design , synthesis, static timing analysis and verification in verilog for page ... an exciting opportunity for you. ESSENTIAL DUTIES AND RESPONSIBILITIES: + Architect and design circuits at transistor level and gate level for leading-edge 3D NAND… more
    SanDisk (07/17/25)
    - Related Jobs
  • Senior Engineer - Physical

    CDM Smith (San Jose, CA)
    …**Business Unit:** IND **Job Description:** As a Senior Substation Engineer - Physical , you'll lead the design and execution of extra high voltage (EHV) ... your expertise in a collaborative environment. Job Description: Electrical Engineer - Physical Lead the design...employment has been made in the United States. The timing of when background checks will be conducted on… more
    CDM Smith (09/27/25)
    - Related Jobs
  • ASIC Engineer , Implementation

    Meta (Sunnyvale, CA)
    …for Power, Performance, and Area 17. 2. Floor Planning and Placement 18. 3. Physical Design Execution for Clock Tree Synthesis and Routing optimization 19. 4 ... Job" online on this web page. **Required Skills:** ASIC Engineer , Implementation Responsibilities: 1. Run logic/ physical synthesis...for Timing , Area, and Power. 2. Debug timing /area/congestion issues and resolve w/ RTL & physical more
    Meta (09/20/25)
    - Related Jobs