- Ampirical (San Ramon, CA)
- **Description** We'd love to have you join our team as a Substation Engineer in San Ramon, CA. **Company Overview:** Ampirical has been committed to improving and ... of solutions to fit the client's need. **Job Summary:** The Substation Engineer works within a multi-discipline team to develop efficient and reliable design… more
- Amazon (Cupertino, CA)
- …- come build the future with us! Key job responsibilities * Perform physical design for Amazon's machine learning custom silicon solutions * Participate in various ... aspects of physical design: full chip floorplanning, circuit analysis, power/clock distribution,...timing optimization, place and route, power integrity analysis, and physical verification * Write Tcl or PERL scripts to… more
- NVIDIA (Santa Clara, CA)
- …choice to join our dynamic team today! We are actively looking for Physical design Engineers with RTL2GDS experience to implement complex high performance and low ... in functional, Timing ECO's and netlist formal verification. + Physical verification- ERC, DRC, LVS etc. What we need...equivalent experience. + 6+ years of hands-on experience in Physical design. + Place and route tool experience with… more
- Capgemini (Sunnyvale, CA)
- **About the job you're considering** We're looking for a collaborative Physical Design Engineer to help drive the next generation of AMS (Analog Mixed Signal) ... technical excellence, and continuous innovation. **Your role** + Develop the physical design of digital blocks across block-level and full-chip AMS implementations… more
- Microsoft Corporation (Santa Clara, CA)
- …and deliver significantly superior performance compared to CPU-based alternatives We're seeking a Physical Design Engineer . As part of our DPU silicon team in ... Santa Clara, you'll take on all aspects of Physical Design from RTL to GDS signoff. You'll tackle...important designs and drive them tapeout, meeting all timing, physical , electrical, and manufacturing requirements: + Perform early design… more
- NVIDIA (Santa Clara, CA)
- …clocks, DFT, power distribution, timing, and place & route. Previous experience as a physical design engineer would be ideal. + Proficiency in C++ + Some ... times per day. We are seeking a CAD R&D Engineer excited to innovate in algorithms related to ECO...time, this role can expand to other areas of physical design implementation and analysis tools + As with… more
- NVIDIA (Santa Clara, CA)
- We are now hiring for a Senior CAD Engineer . NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the ... Technologies Group is looking to hire a Senior CAD Engineer in our Standard Cell Library development team. Do...are growing fast. If you're a creative and autonomous engineer with real passion for technology, we want to… more
- Amazon (San Diego, CA)
- …to unserved and underserved communities around the world. As a Modem Software Design Engineer you will be a part of the team participating in the definition of ... broadband wireless modem. You will participate in all phases of physical layer software development, from architecture design, through requirements, implementation,… more
- NVIDIA (Santa Clara, CA)
- …inventiveness and intelligence. What you will be doing: + Developing innovative physical design methodologies for implementation of GPU, CPU and SOCs, with emphasis ... PPA (Power, Performance, Area) and runtime improvement of the physical design flow on advanced technology nodes + Develop...(or equivalent experience) + Minimum 7 years' experience in Physical Design Engineering + Proven track record of PPA… more
- quadric.io, Inc (Burlingame, CA)
- …What We Expect: Initiative, Collaboration, Completion Role As a member of our physical design methodology team you will be tasked with developing physical ... design methodologies and automation scripts for multiple design configurations across multiple process nodes. Responsibilities + Develop Quadric processor IP implementation scripts from RTL to GDS across multiple advanced process nodes. + Preform test chip… more