- Google (Mountain View, CA)
- …learning accelerators and compute cores. + Experience in micro architecture, power and performance optimization. + Experience in interconnect/fabric, caching ... TPU (Tensor Processing Unit) architecture for next-generation tensor SOC to boost performance , power efficiency and area optimization based on machine learning… more
- Amazon (Sunnyvale, CA)
- …SoC architects, IP developers and physical design teams to develop SoCs that meets the power , performance and area goals for Amazon devices. You will design the ... - Experience in RTL coding (Verilog/System Verilog) and debug, as well as performance / power /area analysis and trade-offs - Experience in closing full-chip and… more
- Meta (Sunnyvale, CA)
- …cross functional teams to ensure our custom silicon developments meet the challenging power , performance and area requirements needed for our wearable products. ... to ensure seamless integration and secure QOR 3. Optimize for power , performance , and area (PPA) using industry-standard tools and methodologies 4. Contribute… more
- Amazon (Sunnyvale, CA)
- …- Work with RTL/logic designers to drive architectural feasibility studies, explore power - performance -area tradeoffs for physical design closure at the block and ... services to deliver quality first pass silicon that meets all performance , power and area goals. - Contribute to developing physical design methodologies… more
- Broadcom (Irvine, CA)
- …performance blocks Timing closure of the blocks with best PPA ( power / performance /area) Debug LVS/DRC/ERC errors with verification tool Analyze the trade-offs ... working with advanced semiconductor technologies. Experience in implementing low power and high- performance cores Excellent communication and cross-functional… more
- NVIDIA (Santa Clara, CA)
- …designs to production is a requirement. + Shown experience in the following areas: Power , Performance and Area improvement Initiatives is a plus. + Already a ... participate in establishing physical design methodologies, flow automation, chip floorplan, power /clock distribution, chip assembly and P&R, timing closure. + Craft… more
- Amazon (Sunnyvale, CA)
- …suitable for being implemented by junior engineers -Evaluate 3rd party IP blocks -Estimate power , performance , and area for significant IPs early in design cycle ... validation. The team works backwards from customer requirements to build super-low power , energy efficient designs that include the latest in AI, video processing,… more
- Meta (Sunnyvale, CA)
- …Meta's vision through Virtual Reality (VR) and Augmented Reality (AR). The compute performance and power efficiency requirements of Virtual and Augmented Reality ... Responsibilities: 1. Contribute to ASIC digital uArchitecture and design for low- power machine learning hardware accelerator 2. Assist performance / power… more
- Google (Mountain View, CA)
- …your deep technical expertise in design and uArch to create the most advanced power and performance efficient mobile coherent systems. Your work will have a ... + Explore and evaluate different uArch and design choices for power and performance efficient coherent and non-coherent memory systems. + Author hardware uArch… more
- Amazon (Cupertino, CA)
- …a key member of the ASIC design team, you will implement and deliver high performance , area and power efficient RTL to achieve design targets and specifications. ... design, microarchitecture or architecture to make trade-offs based on features, power , performance or area requirements. - Develop micro-architecture, implement… more