- Meta (Sunnyvale, CA)
- …for individuals with experience in physical design from RTL to GDSII in low power and high- performance designs to build efficient System on Chip (SoC) and ... end-to-end IP or integration of ASIC/SoC design and point out lower power and higher performance trade-offs 5. Interface with the RTL design team to drive design… more
- Microsoft Corporation (Mountain View, CA)
- …and design engineers to define and deliver differentiating custom IPs which bring high power , performance , and area advantages to the Azure Cloud. We are looking ... advanced process DTCO knobs + Devise methodologies for statistical analysis and timing/ power /EMIR characterization + Run quality assurance checks on IP collateral +… more
- NVIDIA (Santa Clara, CA)
- …and many innovative custom macros. + Apply circuit techniques to improve the power , performance and area utilization of the various communication link designs ... + Hands on experience in design and analysis of low power circuits, eg power gating, decaps, multi-vt is required. + Understanding of Design-for-test (DFT)… more
- Meta (Burlingame, CA)
- …3. Lead hardware bring-up, peripheral drivers and communication, silicon integration, and power and performance management and optimization efforts 4. Debug ... issues that span multiple layers from kernel to application 5. Profile performance problems and drive optimizations across the entire software stack 6. Analyze,… more
- Meta (Sunnyvale, CA)
- …Augmented Reality (AR) and Virtual Reality (VR) devices and platforms. The compute performance and power efficiency requirements of these devices require custom ... to enable SoC and system architecture exploration by instrumenting models for power and performance metrics, allowing for data-driven design decisions and… more
- Meta (Sunnyvale, CA)
- …devices that leverage Mixed Reality (MR) and Augmented Reality (AR). The compute performance and power efficiency requirements of Mixed and Augmented Reality ... chassis generators 3. Work cross-functionally with SoC and IP architecture, performance / power modeling, logic design and verification, physical implementation,… more
- NVIDIA (Santa Clara, CA)
- …be doing: + Analyze pre-production silicon in innovative process technologies for performance , power , yield, and quality to define groundbreaking products as ... and products. + Architect crucial next-generation product features vital for performance , power optimization, and management techniques from feature definition… more
- NVIDIA (Santa Clara, CA)
- …with pre-production silicon in brand-new process technologies to characterize and optimize performance , power , yield, and quality for groundbreaking products. + ... + Design essential next-generation product features that are vital for performance , power optimization, and management techniques from feature definition… more
- Google (Sunnyvale, CA)
- …Integration, from early architecture phase through tapeout. + Knowledge of high performance and low- power design techniques. + Knowledge of ASIC Verification, ... for Tensor Processing Unit (TPU) Compute, you will develop high performance and low power hardware to enable continuous innovations in TPUs. In this role,… more
- NVIDIA (Santa Clara, CA)
- …+ Familiarity with circuit design, noise characterization, product binning methods, and/or performance / power optimization techniques. Ways to stand out from the ... NVIDIA is the industry leader in high performance computing, gaming and AI. Our GPUs and...correlation strategies and roadmap in areas of Speed and Power between design and silicon. You will collaborate with… more