- Amazon (Cupertino, CA)
- …As an ASIC Design Engineer, you will: * Develop and implement high- performance , area and power -efficient RTL designs to meet project specifications ... of designs, microarchitectures, and architectures to optimize trade-offs between features, power consumption, performance , and area requirements * Create… more
- Amazon (Sunnyvale, CA)
- …match or exceed SOTA benchmarks while meeting edge deployment constraints (memory, latency, power ) - Build tools for modeling and performance evaluation to ... enable power , performance , cost options and trade offs - Publish in open source and present on Amazon's behalf at key ML conferences - eg NeurIPS, ICLR, MLSys Basic Qualifications - 3+ years of building machine learning models for business application… more
- NVIDIA (Santa Clara, CA)
- …of the art in deep learning performance and efficiency + Analyze performance , cost and power trade-offs by developing analytical models, simulators and test ... We are now seeking a Senior Deep Learning Performance Architect! NVIDIA is looking for outstanding ... Performance Architect! NVIDIA is looking for outstanding Performance Architects with a background in performance … more
- Google (Sunnyvale, CA)
- …be creating the initial physical layout of a chip top-level; defining block sizing/placement, power grids, and clock distribution to meet performance , power , ... providing recommendations and assessments of process node tradeoffs to meet performance , power , area, and cost goals. Information collected and processed as part… more
- Capgemini (Santa Clara, CA)
- …software and firmware teams. + Enhance virtual platforms with instrumentation for power , performance , and architectural trade‑off analysis. **Your skills and ... will inform critical architectural decisions and accelerate delivery of high‑ performance silicon that powers immersive, real‑world experiences. + Build SystemC/TLM… more
- Meta (Sunnyvale, CA)
- …on overall system performance 11. 3+ years of experience modeling subsystem power and performance , and using those models to inform in tradeoff analysis ... specifications and drive cross-functional workstream prioritization 2. Define subsystem power consumption modeling, use-case data flow, and latency analysis 3.… more
- NVIDIA (Santa Clara, CA)
- …Systems, Digital Design, VLSI Design , RTL Design , Chip Blueprint, Power and Performance Optimization, Testbench Creation + Computer Architecture, Computer ... Power /Clock Distribution, Packaging, P&R and Timing Closure + Performance , Verification, and Emulation Methodology Depending on the internship role, prior… more
- Amazon (San Diego, CA)
- …in deeply scaled CMOS technologies. * Explore circuit architectures for power /area/ performance trade-offs. * Perform circuit layout, parasitic extraction and ... aspects of SERDES. Strong focus will be on creating power and cost optimized solutions for a given system... and cost optimized solutions for a given system performance . Export Control Requirement: Due to applicable export control… more
- Micron Technology, Inc. (San Jose, CA)
- …development of memory products that are best-in-class in terms of die size, performance , reliability, and power . Our NVEG organization is dedicated to advancing ... product design + Deep knowledge and understanding of high-speed IO circuits performance , power and area optimization, chip architecture/floorplan + Demonstrated… more
- Gilead Sciences, Inc. (Foster City, CA)
- …what to measure, standard definitions, and appropriate targets. + Has experience of real-time performance reporting tools such as Tableau or Power BI. + Can ... external best practices on a global basis. **Specific Job Responsibilities:** **Supplier Performance Management** **_(estimated 70% of role)_** + Has a track record… more