- Cadence Design Systems, Inc. (San Jose, CA)
- …Protium is leading product in FPGA Emulation/Prototyping domain. This role is to design , verification , timing closure and hardware validation of the FPGA IPs. ... gate array intellectual properties (FPGA IPs) for Protium platform, including design , verification , integration, timing closure, documentation and releasing the… more
- Medtronic (San Diego, CA)
- …testing and has a strong background in Design Controls. In addition, the Principal R&D Engineer has driven Design Reviews, inclusive of both New ... in process qualifications including Test Method Validation (TMV) and Design Verification Testing (DVT). This individual is...background in Design Controls. In addition, the Principal R&D Engineer has driven Design… more
- Northrop Grumman (Redondo Beach, CA)
- …is seeking ** Principal / Senior Principal IFC Test Plan Support Systems Engineer ... the Greater Baltimore, MD area** _._ **This requisition may be filled as a** ** Principal IFC Test Plan Support Systems Engineer ** **or** **Senior Principal … more
- Northrop Grumman (San Diego, CA)
- …making history. Northrop Grumman Aeronautics Systems has an opening for a ** Principal Airworthiness Engineer /** **Sr. Principal Airworthiness Engineer ... CA with remote capability.** **This position may be filled by either at the Principal Airworthiness Engineer level OR at the Sr. Principal Airworthiness… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …for front-end coding, scripting and developing flows at all phases of the digital design and functional verification . It is further expected that the candidate ... to: + Digital microarchitecture definition and documentation + RTL logic design , debug and functional verification + Strong background in DSP and algorithms is a… more
- City and County of San Francisco (San Francisco, CA)
- …the minimum qualifications. Application Deadline: Continuous How to Apply: Applications for Principal Information Systems Engineer - Networks Specialty are only ... that integrate these systems together as an enterprise networking backbone. The 1044 Principal Networks Engineer is the highest level in the Engineer… more
- City and County of San Francisco (San Francisco, CA)
- …minimum qualifications. Application Deadline: Continuous How to Apply: Applications for Principal Information Systems Engineer - Applications Specialty are only ... that integrate these systems together as an enterprise networking backbone. The 1044 Principal Applications Engineer is the highest level in the Engineer… more
- Micron Technology, Inc. (Folsom, CA)
- …Daily:** + Responsible for floorplanning the full chip level. + Responsible for design partitioning. + Responsible for top level synthesis with multiple hard macro ... Responsible for developing automate high speed matching routing. + Perform verification like LVS/DRC/Antenna, quality check and support documentation. + Responsible… more
- SanDisk (Milpitas, CA)
- …and full chip circuit simulations to meet all performance specifications. + RTL design , synthesis, static timing analysis and verification in verilog for page ... for you. ESSENTIAL DUTIES AND RESPONSIBILITIES: + Architect and design circuits at transistor level and gate level for...relevant experience. + Knowledge and/or experience in data path design (Nand and/or DRAM) + Knowledge in decoding concept… more
- Northrop Grumman (Manhattan Beach, CA)
- …communications systems, facility design , military aerospace development + ** Principal Systems Engineer ** : Bachelor's degree in Science, Technology, ... life and launch your career today. Northrop Grumman Defense Systems is seeking a ** Principal /Sr. Principal Systems Engineer ** in support of the Sentinel… more