- SpaceX (Sunnyvale, CA)
- …RESPONSIBILITIES: + Responsible for evaluating design readiness for scan insertion through RTL and physical design Scan Design Rule Check (DRC) tools + Integration ... and verification of Design for Test (DFT) fabrics and IP within Subsystems + Running and evaluating scan insertion through synthesis tools and refining scan insertion recipe for maximum coverage + Run ATPG(Automatic Test Pattern Generation) analysis to ensure… more
- Google (Sunnyvale, CA)
- …feasibility studies, develop timing, power and area design goals, and explore RTL /design tradeoffs for physical design closure. + Drive physical design methodologies ... and automation scripts for various implementation steps. + Perform technical evaluations of vendors, process nodes, IP, and provide recommendations. Information collected and processed as part of your Google Careers profile, and any job applications you choose… more
- Broadcom (San Jose, CA)
- …Exposure to Design for test, understanding of scan concept and writing DFT friendly RTL . + Experience in synthesis, CDC, static timing analysis. + Exposure to SDF ... annotated simulations with good understanding of parasitic delays. **Highly Desired Qualifications:** + Good understanding of high speed DSP applications and algorithms. + Prior experience of high speed ADC, FFE, DFE, CDR Adaptation algorithms for PAM4… more
- Microsoft Corporation (Mountain View, CA)
- …(AMBA) Advanced eXtensible Interface (AXI) protocols. + Background in debugging RTL (Verilog) designs as well as simulation and/or emulation environments. + ... Scripting languages such as Zsh, Bash, Python or Perl. + Proficient communication, collaboration and teamwork skills and ability to contribute to diverse and inclusive teams within Microsoft and with external vendors. \#SCHIE **Other requirements:** Ability to… more
- Meta (San Diego, CA)
- …consumer or mobile devices 13. Experience with developing tools to generate RTL 14. Experience with scripting languages like Python to facilitate task automation ... 15. Experience collaborating in a multi-site team environment **Public Compensation:** $146,000/year to $209,000/year + bonus + equity + benefits **Industry:** Internet **Equal Opportunity:** Meta is proud to be an Equal Employment Opportunity and Affirmative… more
- Amazon (San Diego, CA)
- …above in Electrical Engineering, Computer Engineering, or related fields - Experience in RTL coding and debug, as well as performance, power, area analysis and ... trade-offs - Experience programming with at least one software programming language, or experience in embedded development in C/C+- Experience with modern ASIC/FPGA design and verification tools - Knowledge of analog and digital skills Preferred Qualifications… more
- Meta (Menlo Park, CA)
- …data center networking architecture, network system design, micro-architecture, RTL design, Design Verification, Firmware/Software development, Pre-Post silicon ... validation, and Program Management to deliver first-pass functional silicon. **Required Skills:** ASIC Engineer, Networking Architecture and Modeling Responsibilities: 1. Collaborate with architecture engineers to define specifications for one or more… more
- Microsoft Corporation (Santa Clara, CA)
- …of correlation of system on chip (SoC) performance models to RTL implementation. **Post-Silicon Validation** Drives development of tools/scripts and guides team ... to implement silicon debug tools and capabilities, such as crash dumps, register dumps, triggers and tracing, and closed chassis/remote debug. Develops comprehensive, full-chip validation strategy, requirements, environments, tools, and methodologies,… more
- Meta (Sunnyvale, CA)
- …shift of software development 15. Experience with SystemVerilog and C++ to model RTL components and transactors 16. Experience with post-silicon bring up, debug, and ... reproducing issues on emulators 17. Experience with cadence (palladium/protium) and Synopsys (zebu) tools 18. Experience with scripting languages such as Python, Perl and TCL **Public Compensation:** $146,000/year to $209,000/year + bonus + equity + benefits… more
- NVIDIA (Santa Clara, CA)
- …modeling and simulation using Matlab/Simulink, Simplis, Spice, VerilogAMS, mixed-signal RTL +spice, s-parameters, etc. + Knowledge of associated power delivery ... networks. + Familiarity/experience with industry-standard design and EDA tools (Cadence Virtuoso, Allegro) and circuit simulation tools (HSpice, Spectre, Primesim, XA, etc) Ways to stand out from the crowd: + Experience modeling and simulating complex power… more