- Meta (Sunnyvale, CA)
- …Physical Design, and Design Power reviews and provide feedback 2. Contribute to optimizing RTL for some of the IPs to achieve best PPA (Power, Performance, Area), ... and support implementation and physical design of the same 3. Develop scripts, tools, and methods to enhance PPA (Power, Performance, Area) 4. Support and develop EDA Infrastructure, and help improve designer productivity 5. Support Simulation accelerators and… more
- Microsoft Corporation (Santa Clara, CA)
- …of correlation of system on chip (SoC) performance models to RTL implementation. **Post-Silicon Validation** Drives development of tools/scripts and guides team ... to implement silicon debug tools and capabilities, such as crash dumps, register dumps, triggers and tracing, and closed chassis/remote debug. Develops comprehensive, full-chip validation strategy, requirements, environments, tools, and methodologies,… more
- Microsoft Corporation (Mountain View, CA)
- …(AMBA) Advanced eXtensible Interface (AXI) protocols. + Background in debugging RTL (Verilog) designs as well as simulation and/or emulation environments. + ... Scripting languages such as Zsh, Bash, Python or Perl. + Proficient communication, collaboration and teamwork skills and ability to contribute to diverse and inclusive teams within Microsoft and with external vendors. \#SCHIE **Other requirements:** Ability to… more
- Cisco (San Jose, CA)
- …as experience with compilation, debug, performance testing. + Prior experience with RTL development for Emulation prototypes. + Prior experience with C/C++ and TCL ... infrastructure development. + Prior experience with System debug tools like gdb, waveform debuggers. **Preferred Qualifications:** + Experience with scripting programs (eg, Python, Perl or similar) + Prior experience with UVM and System Verilog. + Post Silicon… more
- SpaceX (Sunnyvale, CA)
- …results + Experience with scripting languages, eg Python for automation + RTL design, chip bring-up, and post-silicon validation experience + Ability to work ... in a dynamic environment with changing needs and requirements ADDITIONAL REQUIREMENTS: + Must be willing to work extended hours and weekends as needed COMPENSATION AND BENEFITS: Pay range: Design Verification Engineer/Level I: $130,000.00 - $155,000.00/per… more
- Amazon (San Diego, CA)
- …(EVM, ACRL, OOB emissions) - Experience with bit-accurate modeling to match RTL implementations, emulations, FW development - Familiarity with phased array systems ... and phased array performance optimization techniques - Experience in silicon bring-up in the lab and using lab equipment such as vector spectrum analyzer, signal generators, high speed scopes and logic analyzers Amazon is an equal opportunity employer and does… more
- NVIDIA (Santa Clara, CA)
- …the future direction of the methodology for the testbench + Partner closely with RTL and architecture teams to help refine the microarchitecture plans to ensure that ... changes to the design are verifiable + Architect and plan the verification strategy and execution for sub-system features impacting your unit + Support post-silicon validation activities + Harness cutting-edge AI to accelerate testbench development, task… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …Electrical Engineering, Computer Engineering, or a similar major. * Experience with ASIC / RTL / HW Development * Interest and knowledge of verif / post silicon ... bringup The annual salary range for California is $88,900 to $165,100. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation… more
- Cisco (Milpitas, CA)
- …Take ownership of complex FPGA sub-modules, from micro-architecture definition to RTL implementation using Verilog/SystemVerilog or VHDL. + Design & Architecture: ... Define, architect, and implement high-performance digital logic using Hardware Description Languages (Verilog/SystemVerilog) for FPGAs. + Verification: Develop comprehensive, self-checking testbenches and environments to verify FPGA functionality at the block… more
- Microsoft Corporation (Santa Barbara, CA)
- …specific IC design, physical design, physical verification, register transfer level ( RTL ) to graphic data system (GDS) flow. + Experience with industry-standard ... integrated circuit design tools, eg Cadence, Altium, and RF, mixed-signal and integrated-circuit simulation tools, eg Ansys, Sigrity, Comsol. + Experience with industrial semiconductor device design and fabrication processes and tools like process design kits… more