• Emulation Engineer, AWS Annapurna Labs

    Amazon (Cupertino, CA)
    …learn about system flows and execute them on emulation framework * Debug RTL failures associated with chip functionality * Proficient with using various emulation ... debug technologies * Knowledge of using gdb and other techniques to debug software failures * Work with vendors to ensure emulation tool chain is up to date with latest technologies A day in the life As an emulation engineer, you would be working closely with… more
    Amazon (07/29/25)
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  • Google Merch Program Manager

    Acosta Group (Mountain View, CA)
    …Support planning for global installation, maintenance, refresh and disposition of various merchandising elements including fixtures, demos, security and demo ... software. Create, enforce and report on new processes for merchandising compliance and deployment tracking. **RESPONSIBILITIES** **Overall Responsibilities:** Manage planning and communication of in-store merchandising programs including demo units, demo… more
    Acosta Group (07/26/25)
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  • Sr. Physical Design Methodology Engineer,…

    Amazon (Cupertino, CA)
    …compute and storage utilization for physical design work. Interface directly with RTL , Physical Design, Package Design, DFT teams to improve methodologies and ... efficiencies. Be able to independently troubleshoot digital tool flow usage and deploy solutions; Fluent in scripting languages such as TCL, Python, etc. and able to build scalable and efficient flows to support parallel design developments Create Dashboard… more
    Amazon (07/26/25)
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  • Senior GPU Memory Architect

    NVIDIA (Santa Clara, CA)
    …+ Debug power, performance, and functional issues with high-level models, RTL simulation and emulation, silicon, and systems. + Collaborate with outside ... partners on system infrastructure. What we want to see: + 10+ yrs of experience in CPU/GPU architecture, memory systems design with a focus on energy efficiency in the system. + Bachelors in Electrical Engineering, Computer Science, or related field (or… more
    NVIDIA (07/25/25)
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  • Senior ASIC Power Engineer

    NVIDIA (Santa Clara, CA)
    …+ Execute and deliver fully verified, high performance, area and power efficient RTL to achieve design targets + You will be working with architects, designers, ... verification and VLSI teams to accomplish your tasks​ What we need to see: + BS or MS in electrical engineering or computer science or equivalent experience + 8+ years of experience in processor or other related high performance designs + Expertise in… more
    NVIDIA (07/24/25)
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  • Sr. SoC Design - EM/IR, Hardware Compute Group

    Amazon (Sunnyvale, CA)
    …of entire design process from Design specification, defining architecture, micro-architecture, RTL design and functional verification * Experience with DFT and DFM ... flows Amazon is an equal opportunity employer and does not discriminate on the basis of protected veteran status, disability, or other legally protected status. Los Angeles County applicants: Job duties for this position include: work safely and cooperatively… more
    Amazon (07/24/25)
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  • Sr. SDE C/C++ Hardware/Software Co-Design, Machine…

    Amazon (Cupertino, CA)
    …of maintainable, documented and well tested software - Close collaboration with RTL designers, design verification engineers, and other software teams - Mentoring of ... software engineers on best practices, computer architecture and software design choices Basic Qualifications - 7+ years of non-internship professional software development experience - 7+ years of programming with at least one software programming language… more
    Amazon (07/24/25)
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  • C/C++ Hardware / Software Co-Design SDE, Machine…

    Amazon (Cupertino, CA)
    …improved upon, documented, tested, and reused - Close collaboration with RTL designers, design verification engineers, other software teams and customers Basic ... Qualifications - 3+ years of non-internship professional software development experience - 2+ years of non-internship design or architecture (design patterns, reliability and scaling) of new and existing systems experience - Experience programming with at… more
    Amazon (07/19/25)
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  • IC Physical Design Flow, Principal Solutions…

    Cadence Design Systems, Inc. (San Jose, CA)
    …Route (Innovus, ICC2, Fusion Compiler) + Exposure and experience with Synthesis (Genus, RTL Compiler, Design Compiler) + Experience with EDA tools in the IC digital ... implementation & signoff flows (STA tools) + Strong STA and SDC debugging abilities are required. + Low power analysis, Clock design/analysis and hands-on 7/5nm technology node experience a plus. + Automation skills using Perl, Tcl and shell scripting… more
    Cadence Design Systems, Inc. (07/18/25)
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  • Staff Digital Verification Engineer

    Northrop Grumman (San Diego, CA)
    …12 years with an MS degree; 9 years with PhD. + Experience in RTL design and verification methodologies for wireless systems + FPGA development process experience ... (requirements definition, conceptual design, detailed design, verification, and production release) + Experience with Electronic Design Automation (EDA) Tools: QuestaSim + Experience developing verification plans, test benches, bus functional models, and HW-SW… more
    Northrop Grumman (07/18/25)
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