• IC Physical Design Flow, Principal Solutions…

    Cadence Design Systems, Inc. (San Jose, CA)
    …Route (Innovus, ICC2, Fusion Compiler) + Exposure and experience with Synthesis (Genus, RTL Compiler, Design Compiler) + Experience with EDA tools in the IC digital ... implementation & signoff flows (STA tools) + Strong STA and SDC debugging abilities are required. + Low power analysis, Clock design/analysis and hands-on 7/5nm technology node experience a plus. + Automation skills using Perl, Tcl and shell scripting… more
    Cadence Design Systems, Inc. (07/18/25)
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  • Staff Digital Verification Engineer

    Northrop Grumman (San Diego, CA)
    …12 years with an MS degree; 9 years with PhD. + Experience in RTL design and verification methodologies for wireless systems + FPGA development process experience ... (requirements definition, conceptual design, detailed design, verification, and production release) + Experience with Electronic Design Automation (EDA) Tools: QuestaSim + Experience developing verification plans, test benches, bus functional models, and HW-SW… more
    Northrop Grumman (07/18/25)
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  • FPGA Engineer (Starship Electronics)

    SpaceX (Hawthorne, CA)
    …digital designs + Experience in different stages of FPGA development: RTL design, verification, synthesis, timing analysis, lab bring up/validation + Experience ... integrating logic onto SoC platforms and designing high-throughput PS/PL interfaces + Experience developing firmware for Xilinx FPGA platforms using the Xilinx toolchain + Experience developing and testing high reliability, safety critical, and fault tolerant… more
    SpaceX (07/15/25)
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  • VLSI CAD Engineer, ECO Tools - New College Grad

    NVIDIA (Santa Clara, CA)
    …incremental scan insertion, power hookup, placement, timing optimization, etc. + Educate RTL teams on best practices that you identify and advance. + Help ... develop GUIs for design visualization and other tools to boost designer productivity + Over time, this role can expand to other areas of physical design implementation and analysis tools + As with any software engineering team, we do write a lot of code, but… more
    NVIDIA (07/14/25)
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  • Technical Sourcer

    Silvus Technologies (Los Angeles, CA)
    …SKILLS AND ABILITIES + Experience sourcing for niche roles (eg FPGA / RTL Design, AI/ML, Embedded Security, RF Design Engineering, Cybersecurity, Defense Business ... Development, Sales Engineering, etc.). + Strong understanding of complex engineering principles and the ability to effectively communicate technical requirements to candidates. + Proven experience in talent sourcing or agency recruitment with success in… more
    Silvus Technologies (07/12/25)
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  • Senior Firmware Bringup Engineer

    NVIDIA (Santa Clara, CA)
    …6+ years of proven experience in Boot architecture and firmware design. + Excellent RTL and digital design skills + Experience with high-speed IO interface is a ... plus. + Good understanding and coding skills in C/ C++/Python + Understanding of data structures. + Knowledge in ASIL process and flow will be an added advantage + Working knowledge of PC systems, windows OS, and Linux. + Excellent debugging skills. Able to… more
    NVIDIA (07/11/25)
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  • Senior ASIC Verification Engineer - GPU

    NVIDIA (Santa Clara, CA)
    …the future direction of the methodology for the testbench + Partner closely with RTL and architecture teams to help refine the microarchitecture plans to ensure that ... changes to the design are verifiable + Architect and plan the verification strategy and execution for sub-system features impacting your unit + Support post-silicon validation activities What we need to see: + BS or MS in electrical engineering or computer… more
    NVIDIA (07/11/25)
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  • Design Verification Engineer

    Capgemini (Santa Clara, CA)
    …and Python to improve efficiency and consistency. + Perform failure analysis of RTL and gate-level simulations, collaborating with design teams to resolve issues. + ... Create and execute low-power test cases using UPF or CPF to validate SoC power intent. + Simulate real-world use-case scenarios in partnership with system architects. + Drive continuous improvement by identifying verification gaps and enhancing methodologies.… more
    Capgemini (07/09/25)
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  • Senior ASIC Design Engineer, Project Kuiper

    Amazon (San Diego, CA)
    …wireless system architecture in silicon from system specification to chip specification to RTL to optimizing timing / power to chip level validation . Develop ... solutions optimizing customer experience (throughput, latency, and availability) while meeting power and cost constraints . Drive high quality designs for first-time right silicon solutions, and meeting the power objectives . Create standalone verification… more
    Amazon (07/09/25)
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  • Design Engineering Director

    Cadence Design Systems, Inc. (San Jose, CA)
    …standards reliability qualification & specification + Expert level knowledge in Verilog RTL coding for FPGA, python,C/C++ The annual salary range for California is ... $178,500 to $331,500. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a… more
    Cadence Design Systems, Inc. (07/09/25)
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