- Amazon (Sunnyvale, CA)
- …through the various design phases of Silicon development from architecture definition, RTL design, Verification, IP design, Physical design, silicon bring up, test, ... characterization, quality, reliability and post silicon management. About the team Basic Qualifications - 5+ years of technical product or program management experience - 7+ years of working directly with engineering teams experience - 3+ years of software… more
- Applied Materials (Santa Clara, CA)
- …* Design and implement FPGA logic using Vivado, IP Integrator, and Vitis. * Develop RTL modules in VHDL/Verilog for Zynq PL or Xilinx FPGA. * Build and integrate ... custom IP cores and AXI interfaces. * Implement HW-SW co-design using ARM processors on Zynq SoCs. * Implement xDMA, memory IP to realize data transfer between PS and PL. * Implement high-speed IO to realize data transfer between different FPGAs. **CMOS Sensor… more
- Amazon (Cupertino, CA)
- …improved upon, documented, tested, and reused - Close collaboration with RTL designers, design verification engineers, other software teams and customers Basic ... Qualifications - 3+ years of non-internship professional software development experience - 2+ years of non-internship design or architecture (design patterns, reliability and scaling) of new and existing systems experience - Experience programming with at… more
- Western Digital (Roseville, CA)
- …Develop comprehensive test plans and maintain thorough documentation. Conduct RTL code coverage analysis and implement enhancements to improve verification ... completeness. Join our team of experts and make a difference in an exciting career opportunity! **Minimum Requirements:** + Familiar with digital design, design verification, and gate-level simulation. + Familiar with Verilog or System-Verilog and UVM as part… more
- Oracle (Santa Clara, CA)
- …+ _Experience with Simulation/Verification tools such as Synopsys VCS._ + _Experience with RTL linter tools such as Real Intent's Ascent Lint._ + _Experience with ... I2C/SPI/eSPI/PMBUS/SVID/SGPIO/etc communication bus is preferred._ + _Strong knowledge and application of high-speed design methodologies for FPGA logic._ + _Solid understanding of digital design principles and synchronous design techniques._ + _Experience… more
- Oracle (Santa Clara, CA)
- …experience. Use of FPGAs in a hardware design context, and/or RTL /gateware implementation. \#LI-SM18 Disclaimer: **Certain US customer or client-facing roles may ... be required to comply with applicable requirements, such as immunization and occupational health mandates.** **Range and benefit information provided in this posting are specific to the stated locations only** US: Hiring Range in USD from: $120,100 to $251,600… more
- Broadcom (San Jose, CA)
- …as the primary architectural liaison across diverse engineering teams. Strong hands-on RTL and scripting knowledge is a must. **Key Responsibilities** + Bandwidth & ... Power Analysis: Lead comprehensive power and bandwidth analysis for architectural trade-offs. Develop models to predict system performance and power consumption (uW/MHz) and make data-driven decisions to optimize the SoC PPA (Power, Performance, Area). +… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …and communication skills. Preferred / Optional Skills + Exposure to STA and RTL flows would be beneficial. + Familiarity with advanced mixed-signal verification and ... system simulation tools is a plus. Why Join Us? + Work on cutting-edge memory technologies impacting next-generation systems. + Collaborate with global teams and industry-leading customers. + Competitive compensation and benefits package. + Opportunities for… more
- Cisco (San Jose, CA)
- …Lead with a primary focus on Design-for-Test. You will work with Front-end RTL teams, backend physical design teams to understand chip architecture and drive DFT ... requirements early in the design cycle. As a member of this team you will also be involved in crafting groundbreaking next generation networking chips. You will help lead to drive the DFT and quality process through the entire Implementation flow and post… more
- Broadcom (San Jose, CA)
- …verifying designs at system level and block level. + Fluent knowledge of RTL verification methodologies including System Verilog. + Strong experience in ASIC design ... verification flows and DV methodologies + Strong working knowledge of object oriented verification languages (OVM, UVM, etc.), C/C++, Perl, and scripting skills. + Strong and independent design debugging capability. + Strong verbal and written communication… more