- Microsoft Corporation (Mountain View, CA)
- …solutions, automation, and quality assurance checks across front-end areas like RTL & VIP Design, Design Verification, Validation, DFT, Emulation, Design Synthesis, ... RTL Power Anaysis, PD Handoff and SoC integration. This...Timevision, Fishtail, Formality/LEC, Genus, Fusion Compile. - Expertise in RTL power/UPF linting flows like Power Artist/Jules, VCLP. -… more
- Cisco (San Jose, CA)
- …and quality process through the early product life cycle: the architecture definitions, RTL implementation and quality checks. You will also be engaged in relevant ... in-system test, debug and diagnostics needs of the design. + Lead the RTL implementation from the architecture specifications and required RTL quality checks… more
- NVIDIA (Santa Clara, CA)
- …a dedicated and motivated Software developer with particular interest in algorithms and RTL Design. Understanding both Software and Hardware principles will be a key ... doing: + Architect, design, develop and support tools for RTL generation across all NVIDIA products + Architect automated...automated connectivity, auto logic insertion and post processing Verilog RTL + Improve quality of existing tools and flows… more
- Broadcom (San Jose, CA)
- …require in-depth knowledge and expertise in all Physical Design aspects of taking RTL to silicon tape-out. **Responsibilities include, but are not limited to the ... Physical Verification, and Timing Closure + Setup and Synthesizing RTL + Timing closure through various methods and strategies...Flow and Methodology Development + Collaborating with IC Design RTL Engineers + Must work in person at our… more
- Google (Sunnyvale, CA)
- …practical experience. + 7 years of experience with physical design (eg from RTL to GDSII, including key stages like floorplanning, place and route, and timing ... an ASIC Physical Design Engineer, you will collaborate with RTL , Design for Testing (DFT), Floorplan, and full-chip Signoff...closure of the full chip and individual blocks from RTL -to-GDS. + Collaborate with internal logic and internal and… more
- Amazon (Cupertino, CA)
- …level by modeling and estimating power at every stage of the design from early RTL to final netlist and by driving ways to reduce power consumption of our machine ... power analysis & modelling at various stages of design ( RTL to gate level netlist) - Develop and maintain...PowerArtist or similar - Ability to give feedback to RTL designers and Physical Designers on how to reduce… more
- NVIDIA (Santa Clara, CA)
- …+ Use internally developed tools and industry standard pre-silicon gate-level and RTL power analysis tools, to help improve product power efficiency. + Develop ... that warrant more scrutiny. + Interact with architects and RTL designers to help them interpret their power data...principles, including knowledge of Power Artist, PTPX (Prime Power RTL , RTL Architect). + Good verbal/written English… more
- NVIDIA (Santa Clara, CA)
- …will implement, document and deliver high performance, area and power efficient RTL to achieve design targets and specifications. + Analyze architectural trade-offs ... performance requirements and system limitations. + Craft micro-architecture, implement in RTL , and deliver a fully verified, synthesis/timing clean design. +… more
- NVIDIA (Santa Clara, CA)
- …vital part of the GPU Design team, detailing, implementing, and delivering verified RTL to meet design targets. + Analyze architectural trade-offs based on features, ... performance requirements and system limitations. + Craft micro-architecture, implement in RTL , and deliver a fully verified, synthesis/timing clean design. + Support… more
- Teledyne (Goleta, CA)
- …and block diagrams. + Creating risk assessments and traceability matrices. + RTL Front-End Design + Behavioral modeling of digital controllers (eg, pixel readout ... for ASIC modes. + Clock domain crossing and power-aware RTL coding (asynchronous resets, and multi-clock domains). + Modular...corners. + DRC, LVS, extraction and signoff. + Perform RTL Verification & Simulation as needed + Functional verification… more