- NVIDIA (Santa Clara, CA)
- …- from early modeling to silicon validation. You will collaborate with architecture, RTL , physical design, and validation teams to ensure our CPUs meet aggressive ... + Pre-silicon Power Estimation: Model and estimate CPU power at C-model, RTL , and netlist stages using industry-standard tools. + Power Optimization: Identify… more
- NVIDIA (Santa Clara, CA)
- …will implement, document and deliver high performance, area and power efficient RTL to achieve design targets and specifications. + Analyze architectural trade-offs ... performance requirements and system limitations. + Craft micro-architecture, implement in RTL , and deliver a fully verified, synthesis/timing clean design. +… more
- NVIDIA (Santa Clara, CA)
- …will implement, document and deliver high performance, area and power efficient RTL to achieve design targets and specifications. + Analyze architectural trade-offs ... performance requirements and system limitations. + Craft micro-architecture, implement in RTL , and deliver a fully verified, synthesis/timing clean design. +… more
- Broadcom (Irvine, CA)
- …and/or system requirements prepare detailed design document, timing constraint file RTL coding, Lint checks, CDC, Synthesis, Equivalency checking, STA, RTL ... solving skills as well as hands-on lab debugging experiences Good knowledge of RTL simulation and synthesis. In-depth knowledge for design for low power and design… more
- Google (Sunnyvale, CA)
- …AI/ML-driven systems. As a Physical Design Engineer, you will collaborate with RTL , design for testing (DFT), floorplan, and full-chip Signoff teams. Additionally, ... design and closure of the subchip and individual blocks from RTL -to-GDS. + Collaborate with RTL /Design and physical design (PD) teams to achieve the best… more
- NVIDIA (Santa Clara, CA)
- …+ You are expected to come up with micro-architecture, implement in RTL , and deliver a fully verified, synthesis/timing clean design. + Support post-silicon ... working on ASIC design and development. + Experience in micro-architecture and RTL development of complex designs in Verilog. + Exposure to Digital systems… more
- Meta (Sunnyvale, CA)
- …1. Responsible for top-level or block level uArchitecture definition and RTL implementation 2. Contribute to chip-level integration, verification plan development ... 2+ years of experience as a Digital Design Engineer 9. Experience in RTL coding, synthesis and/or SoC Integration 10. Experience in digital design Micro-architecture… more
- NVIDIA (Santa Clara, CA)
- …run, and debug tests on Architecture models. Support test debug on RTL , emulation, and silicon. + Run simulations to analyze Architectural Vulnerability Factor ... various fault types (eg, transient faults, stuck-at faults) in gate-level netlist, RTL , architectural model, silicon and other environments. What we need to see:… more
- Intel Corporation (Folsom, CA)
- …but are not limited to: + Develops the logic design, register transfer level ( RTL ) coding, and simulation for a CPU required to generate cell libraries, functional ... + Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to...correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features. + Documents… more
- RTX Corporation (El Segundo, CA)
- …Do:** + Requirements capture, ASIC / FPGA digital architecture and design using RTL , timing closure, verification, and system integration + Recommend new tools and ... related field and minimum 5 years of experience + RTL coding and simulation in VHDL or Verilog +...timing closure + Testbench development for the verification of RTL blocks using VHDL or System Verilog + Proficiency… more