• R&D IC Design Engineer

    Broadcom (Irvine, CA)
    …and/or system requirements prepare detailed design document, timing constraint file RTL coding, Lint checks, CDC, Synthesis, Equivalency checking, STA, RTL ... solving skills as well as hands-on lab debugging experiences Good knowledge of RTL simulation and synthesis. In-depth knowledge for design for low power and design… more
    Broadcom (12/30/25)
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  • Digital Design Engineer

    Meta (Sunnyvale, CA)
    …1. Responsible for top-level or block level uArchitecture definition and RTL implementation 2. Contribute to chip-level integration, verification plan development ... 2+ years of experience as a Digital Design Engineer 9. Experience in RTL coding, synthesis and/or SoC Integration 10. Experience in digital design Micro-architecture… more
    Meta (12/20/25)
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  • Datacenter Resiliency Architect - New College Grad

    NVIDIA (Santa Clara, CA)
    …run, and debug tests on Architecture models. Support test debug on RTL , emulation, and silicon. + Run simulations to analyze Architectural Vulnerability Factor ... various fault types (eg, transient faults, stuck-at faults) in gate-level netlist, RTL , architectural model, silicon and other environments. What we need to see:… more
    NVIDIA (12/18/25)
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  • CPU Core Logic Designer

    Intel Corporation (Folsom, CA)
    …but are not limited to: + Develops the logic design, register transfer level ( RTL ) coding, and simulation for a CPU required to generate cell libraries, functional ... + Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to...correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features. + Documents… more
    Intel Corporation (12/17/25)
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  • Principal Electrical Engineer - ASIC/FPGA (Onsite)

    RTX Corporation (El Segundo, CA)
    …Do:** + Requirements capture, ASIC / FPGA digital architecture and design using RTL , timing closure, verification, and system integration + Recommend new tools and ... related field and minimum 5 years of experience + RTL coding and simulation in VHDL or Verilog +...timing closure + Testbench development for the verification of RTL blocks using VHDL or System Verilog + Proficiency… more
    RTX Corporation (12/17/25)
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  • Senior ASIC Design Engineer (NetSec)

    Palo Alto Networks (Santa Clara, CA)
    …+ **Write** clear design and micro-architecture specifications. + **Design** SystemVerilog RTL that meets area, performance, and power targets. + **Verify** your ... features. + **Partner** with physical-design teams: review synthesis/timing reports, rewrite RTL to close critical paths, and consult on floor-planning for… more
    Palo Alto Networks (12/15/25)
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  • Senior ASIC Design Engineer, Hardware Compute…

    Amazon (Sunnyvale, CA)
    …multiple disciplines * Develop detailed design specifications and documentation * Perform RTL coding and synthesis * Work with Partners/Suppliers to optimize and ... plan and coverage reviews The ideal candidate should have experience with RTL development environments and fluency in modern hardware description languages. They… more
    Amazon (12/12/25)
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  • Senior Digital Design Engineer

    BrainChip, Inc. (Laguna Hills, CA)
    …Specification, develop a feasible micro architecture, implement the function using RTL language, verify the functionality, and follow up until completion of ... gather the relevant information, and develop a solution. Use RTL language to design the digital functional modules. Program,...tools to check the functionalities of the designs in RTL and gate level. Collaborate with other team members… more
    BrainChip, Inc. (12/11/25)
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  • FPGA Engineer - Design

    Insight Global (Saratoga, CA)
    …providing strategic direction and implementation in the following areas: * Own FPGA RTL development from blank sheet to flight. * Develop FPGA logical architecture ... HW/SW interfaces between fabric logic and processing subsystems. * Develop FPGA RTL code for Microsemi FPGAs and other manufacturer SoCs in either SystemVerilog… more
    Insight Global (12/07/25)
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  • Senior ASIC Engineer - SDC

    Cisco (San Jose, CA)
    …fullchip timing in multiple timing modes. + Option to also do block level RTL design or block or top-level IP integration. + Helping develop efficient methodology to ... cycle. + Reviewing block level SDCs and clocking diagrams and mentor other RTL design owners on SDC development. + Creating fullchip clocking diagrams and related… more
    Cisco (12/03/25)
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