- NVIDIA (Santa Clara, CA)
- …run, and debug tests on Architecture models. Support test debug on RTL , emulation, and silicon. + Run simulations to analyze Architectural Vulnerability Factor ... various fault types (eg, transient faults, stuck-at faults) in gate-level netlist, RTL , architectural model, silicon and other environments. What we need to see:… more
- NVIDIA (Santa Clara, CA)
- …run, and debug tests on Architecture models. Support test debug on RTL , emulation, and silicon. + Run simulations to analyze Architectural Vulnerability Factor ... various fault types (eg, transient faults, stuck-at faults) in gate-level netlist, RTL , architectural model, silicon and other environments. What we need to see:… more
- NVIDIA (Santa Clara, CA)
- …and Ease of timing closure to innovate and implement new Clocking topologies in RTL . + Collaborate with Physical design and timing team to evaluate Clocking concerns ... + Together with other team members, we deliver clock RTL information to GPU, CPU and SOC verification team,...ability to collaborate with multiple teams. + Experience in RTL design (Verilog), verification and logic synthesis. + Strong… more
- John Deere (Torrance, CA)
- …+ 4 years of experience in create self-checking test environment using UVM to debug the RTL and ensure the functional intent of the DUT + 4 years of experience in ... generate scripts to setup the RTL simulation, regressions + 4 years of experience in...years of experience in perform timing closure for the RTL core logic (FPGA) **Education/Experience** + Bachelor's degree in… more
- Amazon (Sunnyvale, CA)
- …processes - Develop, regress, and deploy digital front end flows including RTL static checks and design verification methodology - Develop, regress and deploy ... digital EDA flow development and/or digital design experience - Familiar with digital RTL code checks and implementation, including Lint, CDC, RDC, SDC - Familiar… more
- NVIDIA (Santa Clara, CA)
- …with 3+, or PhD with 2+ years of experience in DFT, system architecture, or RTL design. + Understanding of fundamental DFT topics, such as, fault modeling, ATPG and ... and dielet/chiplet based designs, and UCIe protocol. + Good understanding of RTL coding principles. + Knowledge of high-speed interface architectures such as PCIe,… more
- NVIDIA (Santa Clara, CA)
- …part of the System ASIC Design team to help develop and improve our RTL and SOC designs + Collaborate with architects, ASIC designers, and verification engineers to ... Boot controllers. + You will be responsible for the RTL design, logic synthesis, and timing analysis of several...design concepts and experience in ASIC design flow including RTL design, verification, logic synthesis and timing analysis +… more
- BrainChip, Inc. (Laguna Hills, CA)
- …Specification, develop a feasible micro architecture, implement the function using RTL language, verify the functionality, and follow up until completion of ... gather the relevant information, and develop a solution. Use RTL language to design the digital functional modules. Program,...tools to check the functionalities of the designs in RTL and gate level. Collaborate with other team members… more
- Amazon (Sunnyvale, CA)
- …As a Physical Design Engineer, you will: - Work with RTL /logic designers to drive architectural feasibility studies, explore power-performance-area tradeoffs for ... other physical design engineers as well as with the RTL /Arch. Teams Basic Qualifications - BS in EE/CS -...EE/CS - 7+ years in ASIC Physical Design from RTL -to-GDSII in FINFET technologies such as 5nm/7nm, 14/16nm -… more
- Amazon (Cupertino, CA)
- …the right trade-offs. Key job responsibilities - Work with RTL /logic designers to drive architectural feasibility studies, explore power-performance-area tradeoffs ... other physical design engineers as well as with the RTL /Arch. teams About the team Inclusive Team Culture Here...- 6+ years in ASIC Physical Design from - RTL -to-GDSII in either 7nm, 14/16nm, 20nm, or 28nm -… more