- Google (Mountain View, CA)
- …and write CPU subsystem architecture specifications. + Lead the collaboration with RTL , design verification, and physical design teams to develop a high performance ... implementation. + Drive performance correlation between the performance model and RTL implementation and perform pre-silicon and post-silicon performance bug triage.… more
- Microsoft Corporation (Mountain View, CA)
- …workload information and working with Micro-architects and Register Transfer Level ( RTL ) team to identify performance bottlenecks. Collaborate across functionally to ... and analysis. + Verify the correlation of the SOC performance models to the RTL implementation. + Work closely with the product architecture System On Chip (SOC)… more
- Google (San Diego, CA)
- …field, or equivalent practical experience. + 8 years of experience with RTL design using Verilog/System Verilog and microarchitecture. + 4 years of experience ... flows and integration requirements for Subsystem Development. + Oversee RTL development, and debug functional/performance simulations. + Meet schedule commitments… more
- Google (Mountain View, CA)
- …and write CPU subsystem architecture specifications. + Lead the collaboration with RTL , design verification, and physical design teams to develop CPU implementation. ... + Drive performance correlation between the performance model and RTL implementation, and perform pre-silicon and post-silicon performance bug triage. Google is… more
- SanDisk (Milpitas, CA)
- …experienced **Digital Physical Design Engineer** to work whole digital SPR flow from RTL to GDS, include Synthesis, DFT scan insertion, PNR, STA timing analysis, ... REQUIRED: + **Experience:** A minimum of 3 years in Physical design digital RTL to GDS flow. + **Education** : Bachelor's or Master's degree in Electrical… more
- Meta (Sunnyvale, CA)
- …organization. We are looking for individuals with experience in physical design from RTL to GDSII in low power and high-performance designs to build efficient System ... point out lower power and higher performance trade-offs 5. Interface with the RTL design team to drive design modifications to resolve congestion/timing issues and… more
- Meta (Sunnyvale, CA)
- …with IP, Design, Implementation, Software, and Product. 4. Lead logic development, develop RTL and drive chip level integration. 5. Supervise the RTL -to-GDS flow ... and assist with synthesis and timing closure to meet frequency, power and area goals. 6. Support the test program development, chip validation, and chip life until production maturity. 7. In addition to working with FPGA engineers to perform early prototyping,… more
- Meta (Sunnyvale, CA)
- …SoC Physical Design Engineer Responsibilities: 1. Physical design implementation from RTL to netlist for complex digital blocks or full-chip designs, responsible ... synthesis (CTS), routing, static timing analysis and signoff 2. Collaborate with RTL design, DFT, verification, and power teams to ensure seamless integration and… more
- Meta (Sunnyvale, CA)
- …or equivalent practical experience 6. 6+ years of experience in micro-architecture and RTL development for complex control and data path IPs OR Experience in SoC ... Micro-architecture, Design and Integration 7. RTL development using Verilog, System Verilog and HLS **Preferred Qualifications:** Preferred Qualifications: 8.… more
- Meta (Sunnyvale, CA)
- …Engineer, Design Responsibilities: 1. Architecture exploration 2. Micro-architecture development 3. RTL development using Verilog, System Verilog and HLS 4. Soft and ... or equivalent practical experience 8. 12+ years of experience in micro-architecture and RTL development for complex IPs or Subsystems 9. Experience in leading the… more