• Principal Digital Engineer

    Renesas (San Jose, CA)
    …peripheral IP, volatile/non-volatile memory IP selection, partitioning of hardware/firmware, RTL design, verification, FPGA prototyping, DFT, and IC qualification. ... memory subsystem, on-chip bus system, DMA and interrupt system + Digital IP RTL design, simulation, and release + Independently handle complicated design tasks or… more
    Renesas (12/23/25)
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  • Principal ASIC Design Engineer (Silicon…

    SpaceX (Sunnyvale, CA)
    …performance requirements and system limitations + Define micro-architecture, implement the RTL in Verilog/System Verilog, integrate that in top level and deliver ... computer engineering, or computer science + 10+ years of experience in RTL implementation and/or FPGA/ASIC development PREFERRED SKILLS AND EXPERIENCE: + Experience… more
    SpaceX (12/22/25)
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  • SoC Silicon Top-Level Floorplan Engineer

    Google (Sunnyvale, CA)
    …advanced nodes. + Experience collaborating with cross-functional teams (eg, architecture, RTL design, synthesis, verification). + 3D IC design experience (eg, ... performance, power, and area (PPA) goals; requiring deep collaboration with architecture, RTL , and synthesis teams; using industry and internal tools; and driving… more
    Google (12/20/25)
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  • ASIC Engineer, Physical Design

    Meta (Sunnyvale, CA)
    …placement and routing, to improve performance and power 5. Work with the RTL design team to understand partition architecture and drive physical aspects early in ... the design cycle 6. Interface with the RTL design team to drive design modifications to resolve congestion/timing issues and implement functional ECO's 7. Use EDA… more
    Meta (12/20/25)
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  • ASIC Engineer Physical Design

    Meta (Sunnyvale, CA)
    …placement and routing, to improve performance and power 5. Work with the RTL design team to understand partition architecture and drive physical aspects early in ... the design cycle 6. Interface with the RTL design team to drive design modifications to resolve congestion/timing issues and implement functional ECO's 7. Use EDA… more
    Meta (12/20/25)
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  • Senior Hardware Engineer- FPGA

    Cisco (Milpitas, CA)
    …of the project. You are an experienced FPGA designer able to write RTL code, run simulations, address timing and other constraints, then generate programming files. ... experience from specification to production. + Experience with Verilog/System Verilog RTL coding + Experience with industry leading FPGA devices and tools.… more
    Cisco (12/20/25)
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  • Senior Circuit Design Engineer

    NVIDIA (Santa Clara, CA)
    …+ Drive the design and physical implementation of custom digital IPs from RTL to layout using industry standard tools and custom design flows. + Collaborate ... power circuits (power gating, decaps, multi-vt, etc..) is a plus. + Experience with RTL , logic synthesis and verification is a plus. + Mixed signal circuit design… more
    NVIDIA (12/18/25)
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  • ASIC Design Engineer, Cloud-Scale Machine Learning…

    Amazon (Cupertino, CA)
    …Engineer, you will: * Develop and implement high-performance, area and power-efficient RTL designs to meet project specifications and targets * Conduct in-depth ... performance, and area requirements * Create microarchitectures, implement SystemVerilog RTL , and deliver synthesis and timing-clean designs with appropriate… more
    Amazon (12/18/25)
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  • Hardware Engineer

    Cisco (Milpitas, CA)
    …requires proficiency in the full FPGA development lifecycle, including independent RTL coding, verification, high-speed design practices, and debugging on hardware. ... ownership of complex FPGA sub-modules, from micro-architecture definition to RTL implementation using Verilog/SystemVerilog or VHDL. + Design Optimization: Actively… more
    Cisco (12/16/25)
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  • SoC Physical Design Engineer

    Google (Sunnyvale, CA)
    …Chip (SoC) Physical Design Engineer, you will collaborate with Register-Transfer Level ( RTL ), Design for Testing (DFT), Floorplan, and full-chip Sign off teams. ... blocks from Register-Transfer Level-to-Graphic Design System . + Collaborate with RTL /Design and Product Development teams to achieve the best Power Performance… more
    Google (12/11/25)
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