- Meta (Sunnyvale, CA)
- …placement and routing, to improve performance and power 5. Work with the RTL design team to understand partition architecture and drive physical aspects early in ... the design cycle 6. Interface with the RTL design team to drive design modifications to resolve congestion/timing issues and implement functional ECO's 7. Use EDA… more
- Meta (Sunnyvale, CA)
- …placement and routing, to improve performance and power 5. Work with the RTL design team to understand partition architecture and drive physical aspects early in ... the design cycle 6. Interface with the RTL design team to drive design modifications to resolve congestion/timing issues and implement functional ECO's 7. Use EDA… more
- Cisco (Milpitas, CA)
- …of the project. You are an experienced FPGA designer able to write RTL code, run simulations, address timing and other constraints, then generate programming files. ... experience from specification to production. + Experience with Verilog/System Verilog RTL coding + Experience with industry leading FPGA devices and tools.… more
- NVIDIA (Santa Clara, CA)
- …+ Drive the design and physical implementation of custom digital IPs from RTL to layout using industry standard tools and custom design flows. + Collaborate ... power circuits (power gating, decaps, multi-vt, etc..) is a plus. + Experience with RTL , logic synthesis and verification is a plus. + Mixed signal circuit design… more
- Amazon (Cupertino, CA)
- …Engineer, you will: * Develop and implement high-performance, area and power-efficient RTL designs to meet project specifications and targets * Conduct in-depth ... performance, and area requirements * Create microarchitectures, implement SystemVerilog RTL , and deliver synthesis and timing-clean designs with appropriate… more
- Cisco (Milpitas, CA)
- …requires proficiency in the full FPGA development lifecycle, including independent RTL coding, verification, high-speed design practices, and debugging on hardware. ... ownership of complex FPGA sub-modules, from micro-architecture definition to RTL implementation using Verilog/SystemVerilog or VHDL. + Design Optimization: Actively… more
- Google (Sunnyvale, CA)
- …Chip (SoC) Physical Design Engineer, you will collaborate with Register-Transfer Level ( RTL ), Design for Testing (DFT), Floorplan, and full-chip Sign off teams. ... blocks from Register-Transfer Level-to-Graphic Design System . + Collaborate with RTL /Design and Product Development teams to achieve the best Power Performance… more
- NVIDIA (Santa Clara, CA)
- …front-end chip implementation process and propose actionable improvements + Ensure high-quality RTL delivery to the physical design team with thorough design quality ... and automation + Strong analytical and problem-solving skills + Expertise in RTL design, SOC integration, and design automation flows + Proficiency in Perl,… more
- NVIDIA (Santa Clara, CA)
- …infrastructure tools used by design engineers for build and verification of architectural, rtl , and gate level designs. As a software engineer, you will craft highly ... and requirements Ways to stand out from the crowd: + Good architecture and RTL design knowledge + Strong expertise in modern C++, compiler, build systems, and… more
- NVIDIA (Santa Clara, CA)
- …of meaningful work experience. + Experience in Computer Architecture and RTL development (Verilog), focused on arbiters, scheduling, synchronization & bus protocols, ... silicon visibility tools. + Great understanding of ASIC design flow including RTL design, verification, logic synthesis, timing analysis and bringup. + Strong… more