• Annapurna Labs at AWS Internships (US) - Machine…

    Amazon (Cupertino, CA)
    …Hardware/Software Integration * Performance Analysis Tools Silicon Innovation & Design * RTL Development for ML Accelerators * Hardware Architecture & Modeling * ... computing 5. Performance analysis and optimization 6. Hardware design ( RTL , Verilog, FPGA development) Preferred Qualifications - Previous internship, research,… more
    Amazon (12/05/25)
    - Related Jobs
  • Senior Architecture Energy Modeling Engineer

    NVIDIA (Santa Clara, CA)
    …for building energy models that integrate into architectural simulators, RTL simulation, emulation and silicon platforms. Key responsibilities include developing ... to debug energy inefficiencies observed in various workloads run on silicon, RTL , and architectural simulators. Identify and suggest solutions to fix the energy… more
    NVIDIA (12/05/25)
    - Related Jobs
  • Lead Application Engineer

    Cadence Design Systems, Inc. (San Jose, CA)
    …MS.or PhD degree in Computer Science, Engineering, or related fieldStrong RTL and Testbench debug skillsExperience in synthesizable coding styleExperience in writing ... and asynchronous interfacesKnowledge of the FPGA development process & tool flow from RTL to bitstream for Xilinx and/or Altera productsHands on experience with lab… more
    Cadence Design Systems, Inc. (12/04/25)
    - Related Jobs
  • R&D Engineer IC Design

    Broadcom (Irvine, CA)
    …+ HDL coding, equivalency checking, STA result review, CDC checks, Lint checks, RTL /gate level simulations & silicon debugging + scripting for various IC design ... + HDL coding, equivalency checking, STA result review, CDC checks, Lint checks, RTL /gate level simulations & silicon debugging + scripting for various IC design… more
    Broadcom (12/03/25)
    - Related Jobs
  • Anchor- Senior Software Engineer

    Ford Motor Company (Sacramento, CA)
    …strong keyboard navigation, screen reader flows, robust localization (including RTL ), and ensure Accessibility compliance. + Data integration: consume REST/GraphQL ... (WCAG 2.2 AA) and hands on internationalization/localization experience (incl. RTL ). + Experience integrating REST/GraphQL services and strong client side… more
    Ford Motor Company (12/03/25)
    - Related Jobs
  • Senior Formal Verification Engineer

    NVIDIA (Santa Clara, CA)
    …sufficient coverage. + Drive formal tools to realize their best performance. + Debug RTL to identify causes of failure scenarios. + Contribute to flow and script ... Experience with Verilog / System Verilog HDLs and able to understand sophisticated RTL quickly. + Experience with formal tools and knowledge of formal verification… more
    NVIDIA (11/27/25)
    - Related Jobs
  • Senior GPU Low Power Architect

    NVIDIA (Santa Clara, CA)
    …and verticals. What you'll be doing: + Invent and innovate low power architectural/ RTL solutions and drive features and roadmaps for improving efficiency of our ... techniques is essential. + Design experience with industry tools such as SystemVerilog RTL , UVM, Verdi, UPF, VCS NLP, Python, C++ are essential. + Cross-discipline… more
    NVIDIA (11/20/25)
    - Related Jobs
  • Chip Integration Engineer

    Broadcom (San Jose, CA)
    …responsible for various key tasks in the areas of chip integration and RTL design of cutting-edge network switch/routing designs. The day-to-day tasks for this ... blocks and working on initial floor plan. 5). Develop Verilog RTL . design verification support, logic synthesis, physical implementation constraints, static timing… more
    Broadcom (11/19/25)
    - Related Jobs
  • IC Design Engineer

    Broadcom (Irvine, CA)
    …Participate in IP level architectural definition including micro-architecture definition + Perform RTL design using Verilog HDL, with an emphasis on performance and ... of relevant industry experience. Advanced degree preferred Must have strong Logic Design, RTL coding (Verilog HDL) and debugging skills Must have an understanding of… more
    Broadcom (11/18/25)
    - Related Jobs
  • ASIC Design Technical Leader - Design & Timing…

    Cisco (San Jose, CA)
    …fullchip timing in multiple timing modes. + Option to also do block level RTL design or block or top-level IP integration. + Helping develop efficient methodology to ... cycle. + Reviewing block level SDCs and clocking diagrams and mentor other RTL design owners on SDC development. + Creating fullchip clocking diagrams and related… more
    Cisco (11/18/25)
    - Related Jobs