- Amazon (San Diego, CA)
- …(EVM, ACRL, OOB emissions) - Experience with bit-accurate modeling to match RTL implementations, emulations, FW development - Familiarity with phased array systems ... and phased array performance optimization techniques - Experience in silicon bring-up in the lab and using lab equipment such as vector spectrum analyzer, signal generators, high speed scopes and logic analyzers Amazon is an equal opportunity employer and does… more
- NVIDIA (Santa Clara, CA)
- …the future direction of the methodology for the testbench + Partner closely with RTL and architecture teams to help refine the microarchitecture plans to ensure that ... changes to the design are verifiable + Architect and plan the verification strategy and execution for sub-system features impacting your unit + Support post-silicon validation activities + Harness cutting-edge AI to accelerate testbench development, task… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …Electrical Engineering, Computer Engineering, or a similar major. * Experience with ASIC / RTL / HW Development * Interest and knowledge of verif / post silicon ... bringup The annual salary range for California is $88,900 to $165,100. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation… more
- SpaceX (Sunnyvale, CA)
- …studies, develop timing, power and area design targets, and explore RTL /design tradeoffs + Resolve design/timing/congestion and flow issues, identify potential ... solutions and drive execution + Run, debug, and fix signoff closure issues in static timing analysis (STA), noise, logic equivalency, physical verification, electromigration and voltage drop BASIC QUALIFICATIONS: + Bachelor's degree in electrical engineering,… more
- Cisco (Milpitas, CA)
- …Take ownership of complex FPGA sub-modules, from micro-architecture definition to RTL implementation using Verilog/SystemVerilog or VHDL. + Design & Architecture: ... Define, architect, and implement high-performance digital logic using Hardware Description Languages (Verilog/SystemVerilog) for FPGAs. + Verification: Develop comprehensive, self-checking testbenches and environments to verify FPGA functionality at the block… more
- Microsoft Corporation (Santa Barbara, CA)
- …specific IC design, physical design, physical verification, register transfer level ( RTL ) to graphic data system (GDS) flow. + Experience with industry-standard ... integrated circuit design tools, eg Cadence, Altium, and RF, mixed-signal and integrated-circuit simulation tools, eg Ansys, Sigrity, Comsol. + Experience with industrial semiconductor device design and fabrication processes and tools like process design kits… more
- SpaceX (Sunnyvale, CA)
- …reports for project tracking and visualizing results/stats + Interface directly with RTL , physical design, package design, DFT and other teams to improve ... methodologies and efficiencies and drive efforts to resolution + Work with EDA tool vendors to evaluate new tools, solve bugs, improve usability, methodology and design flow + Integrate foundry EDA kits into SpaceX environment, drive vendor IP integration into… more
- Meta (Sunnyvale, CA)
- …Machine Learning IPs Silicon development 8. Experience in digital design uArchitecture, RTL coding 9. Experience with methods for partitioning a solution across ... hardware and software, evaluating trade-offs such as speed, performance, power, area 10. Results oriented, proactive with demonstrated creative & critical thinking **Preferred Qualifications:** Preferred Qualifications: 11. Experience in deep learning… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …standards reliability qualification & specification + Expert level knowledge in Verilog RTL coding for FPGA, python,C/C++ The annual salary range for California is ... $178,500 to $331,500. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a… more
- Microsoft Corporation (Mountain View, CA)
- …and Universal Verification Methodology (UVM) + Experience debugging Register Transfer Level ( RTL ) designs as well as simulation and/or emulation environments. + 12+ ... years of experience in design verification + 5+ years experience with lead roles across cross-functional / cross-time-zone engineering teams. + Verification lead experience for an IP or SS related to CPUs, VPUs, GPUs, Direct Memory Access (DMA) engine, Tensor… more