- Cadence Design Systems, Inc. (San Jose, CA)
- …motivated, optimistic, and energetic engineer with a good appreciation of ASIC design methodologies from RTL to GDSII with a strong history of ... technology. This opportunity is for an engagement focused Product Engineer (PE) in the Digital and Signoff Group (DSG)...PPA tuning and Layout experience, having experience of either RTL design and/or associated tool knowledge is… more
- NVIDIA (Santa Clara, CA)
- …of experience in front-end ASIC synthesis and integration. + Deep understanding of Verilog RTL design and digital design principles. + Proven experience with ... as part of the advanced technology team to optimize design tradeoffs and methodology on next generation CMOS technology....You'll Be doing: + As a Front-End ASIC Synthesis Engineer , you will own RTL synthesis and… more
- Amazon (San Diego, CA)
- …world. Come work at Amazon! The Role: As a Sr. DSP and Wireless Systems Engineer working in the Digital RF Systems team, you will be responsible for DSP architecture ... definition, design and simulation of DSP blocks in wireless communication...high throughput for our customers. As a Sr. DSP Engineer , you will engage with an experienced cross-disciplinary staff… more
- Arrow Electronics (San Jose, CA)
- …close **fullchip timing** in multiple timing modes. + Option to also do block level RTL design or block or top-level IP integration. + Helping develop efficient ... **Position:** SDC Engineer (eInfochips Inc) **Job Description:** **Position: SDC ...block level SDCs and clocking diagrams and mentor other RTL design owners on SDC development. +… more
- NVIDIA (Santa Clara, CA)
- …advanced silicon processes. We're responsible for NVIDIA's front-end ASIC software including RTL synthesis, equivalence checking, and early physical design and ... a lasting impact on the world. Are you a computer engineer with a passion for automation of VLSI ASIC design ? Be part of a diverse team creating NVIDIA's chip … more
- NVIDIA (Santa Clara, CA)
- …In-silicon measurement, Reset and Boot controllers. + You will be responsible for the RTL design , logic synthesis, and timing analysis of several modules. + ... is looking for a Senior Reset and Boot ASIC Engineer to join our System ASIC team! NVIDIA has...like Reset or Chip Boot + Solid frontend ASIC design skills, including RTL design ,… more
- NVIDIA (Santa Clara, CA)
- …inventiveness and intelligence. We are seeking a highly skilled Timing Methodology Engineer with expertise in asynchronous timing and I/O interface modeling to ... validating IO timing integrity, and enabling scalable STA methodologies across design hierarchies and technology nodes. We're looking for someone passionate about… more
- NVIDIA (Santa Clara, CA)
- NVIDIA is seeking elite ASIC RTL /Verification ASIC engineers to develop the core Verification and RTL infrastructure of the world's leading GPUs. This position ... team of dedicated Infrastructure engineers continuously upgrades the NVIDIA Hardware design environment. We focus relentlessly on Infrastructure improvement so that… more
- SpaceX (Hawthorne, CA)
- …complex digital designs + Experience in different stages of FPGA development: RTL design , verification, synthesis, timing analysis, lab bring up/validation + ... for versatile, driven, and collaborative engineers. As an FPGA engineer on the satellite digital design team,...an FPGA engineer on the satellite digital design team, you will be designing, developing, and testing… more
- Google (Mountain View, CA)
- … design : hardware-software co- design for ML models, hardware generation and verification, RTL optimization, and system design . + Engage and work in a fast ... to revolutionise AI by applying state-of-the-art AI to Chip Design . We develop research breakthroughs that impact all aspects...to set you up for success as a Research Engineer at Google DeepMind, we look for the following… more