- Cadence Design Systems, Inc. (San Jose, CA)
- …on memory subsystem verification and/or performance analysis* Strong knowledge of ASIC flow, RTL design in Verilog, System Verilog and FPGA design * ... an impact on the world of technology. Senior Applications Engineer - DDR Design IPJob Location: San...opportunities* Run Verilog simulations to enable IP benchmarking* Run RTL synthesis for area and timing analysis* Present IP… more
- Broadcom (Irvine, CA)
- …Account, please Sign-In before you apply.** **Job Description:** **Job Description: IC Design Engineer ** + Participate in IP level architectural definition ... including micro-architecture definition + Perform RTL design using Verilog HDL, with an emphasis on performance and area + Implement multi-power and low-power… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior ASIC Design Engineer - DFX NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked ... or related field. + 5+ years of hands-on experience in SoC architecture, RTL design , and verification. + Strong proficiency in micro-architecture and RTL … more
- Microsoft Corporation (Mountain View, CA)
- …passionate engineers to help achieve that mission. We are looking for a Principal Design Engineer to work in the dynamic Microsoft Artificial Intelligence System ... working on Intellectual Property (IP) microarchitecture specification, Register Transfer Level ( RTL ) design , synthesis, and System on Chip (SOC) integration… more
- Microsoft Corporation (Mountain View, CA)
- …passionate engineers to help achieve that mission. We are looking for a Senior Design Engineer to work in the dynamic Microsoft Artificial Intelligence System on ... working on Intellectual Property (IP) microarchitecture specification, Register Transfer Level ( RTL ) design , synthesis/Lint/CDC/FEV and System on Chip (SOC)… more
- NVIDIA (Santa Clara, CA)
- …you can make a lasting impact on the world. Join NVIDIA as a Senior SoC Design Engineer developing innovative SoC solutions. What you'll be doing: + Work in ... compute, fabric, memory, and attached devices. + Strong background in RTL design developing high-speed digital blocks. + Experience in negotiating solutions… more
- NVIDIA (Santa Clara, CA)
- …logic analyzers and/or other silicon visibility tools. + Great understanding of ASIC design flow including RTL design , verification, logic synthesis, timing ... looking for a Senior Design for Debug (DFD) Architect and Methodology Engineer ! NVIDIA is seeking a DFD Architect to implement hardware and software solutions to… more
- Meta (Sunnyvale, CA)
- …learning, video transcoding and network acceleration. **Required Skills:** ASIC Engineer , Design Responsibilities: 1. Architecture exploration 2. ... and data path IPs OR Experience in SoC Micro-architecture, Design and Integration 7. RTL development using...in SoC Micro-architecture, Design and Integration 7. RTL development using Verilog, System Verilog and HLS **Preferred… more
- NVIDIA (Santa Clara, CA)
- …inventiveness and intelligence. We are now looking for a motivated Senior ASIC Physical Design Engineer , Netlisting to join our dynamic and growing team. If you ... tools. Deep understanding of hardware architecture and hands-on skills in RTL /logic design for timing closure. + Experience in clock-domain-crossing… more
- Meta (Sunnyvale, CA)
- …to Job" online on this web page. **Required Skills:** ASIC Engineer , Implementation Responsibilities: 1. Run logic/physical synthesis using advanced optimization ... and Power. 2. Debug timing/area/congestion issues and resolve w/ RTL & physical designers. 3. Perform power estimation at...domain crossing checks. 9. Understand reset-architecture and work with design & FW teams to develop reset groups and… more