• Senior FPGA Prototyping Engineer

    NVIDIA (Santa Clara, CA)
    …Santa Clara, CA. What you'll be doing: + Build FPGA prototypes by making RTL FPGA -friendly, partitioning the design and taking it through synthesis and ... prototyping platforms. We are now looking for a Senior FPGA Prototyping Engineer to join our Emulation...timing and generate bit streams. + Bring up the design on FPGA prototyping platforms and indulge… more
    NVIDIA (09/09/25)
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  • FPGA Design Engineer

    Arrow Electronics (San Jose, CA)
    **Position:** FPGA Design Engineer **Job Description:** Principal Accountabilities * RTL development for ASIC / FPGA * Responsible for completion of ... front end design flow (spec to RTL / Netlist) * **Annual Hiring Range/Hourly Rate:** $92,200.00 - $203,500.00 Actual compensation offer to candidate may vary… more
    Arrow Electronics (11/14/25)
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  • Hardware Engineer - FPGA

    Cisco (Milpitas, CA)
    …the complexity of system hardware and software interactions. In addition, having experience in FPGA design and can write RTL code, run simulations, address ... fully unified routing and switching portfolio. **Your Impact** The FPGA Engineer will get to work with...designs control path FPGAs for the various boards. The Engineer will interface with diagnostics, software, board design more
    Cisco (11/13/25)
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  • Senior Electrical Engineer - ASIC/…

    RTX Corporation (El Segundo, CA)
    …Will Do:** + Requirements capture, ASIC / FPGA digital architecture and design using RTL , timing closure, verification, and system integration + Recommend ... practices for continuous improvement in the group's ASIC / FPGA design flow + Contribute to engineering...security clearance is required prior to start date. + RTL coding and simulation in VHDL or Verilog +… more
    RTX Corporation (10/28/25)
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  • Electrical Engineer II - ASIC/ FPGA

    RTX Corporation (El Segundo, CA)
    …requirements capture and ASIC / FPGA digital architecture + Implement ASIC / FPGA digital design using RTL + Support verification and system integration ... security clearance is required prior to start date + RTL coding and simulation in VHDL, Verilog, or SystemVerilog...equipment **Qualifications We Prefer:** + Experience using ASIC and/or FPGA design tools (eg Modelsim, Quartus, Vivado… more
    RTX Corporation (10/28/25)
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  • FPGA Engineer , Platforms, Hardware

    Google (Sunnyvale, CA)
    …aboutbenefits at Google (https://careers.google.com/benefits/) . **Responsibilities** + Define and develop Field-Programmable Gate Array ( FPGA ) based ... FPGA Engineer , Platforms, Hardware _corporate_fare_ Google...4 years of experience working in an ASIC or FPGA design technical environment, or 3 years… more
    Google (09/28/25)
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  • Staff FPGA Engineer

    J&J Family of Companies (Santa Clara, CA)
    …of America **Job Description:** **Employer:** Auris Health, Inc. **Job Title:** Staff FPGA Engineer **Job Code:** A011.10925 **Job Location:** Santa Clara, CA ... testing, and functional verification. Collaborate with partners to finalize RTL design requirements. Develop RTL ...experience in the job offered or in a Staff FPGA Engineer -related occupation. This job posting is… more
    J&J Family of Companies (10/11/25)
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  • Senior Staff Signal Processing Engineer

    General Atomics (Poway, CA)
    …Signal Processing Engineer with strong capabilities in systems architecture, RTL level design , verification and validation. This position will work ... The successful candidate will work with a multi-disciplinary team to design , develop, and implement data processing and signal processing algorithms. **DUTIES… more
    General Atomics (10/24/25)
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  • Senior Digital Design Engineer

    BrainChip, Inc. (Laguna Hills, CA)
    BrainChip is seeking a Senior Digital Design Engineer to join a team working on cutting-edge and novel AI hardware. The primary job function is to work with team ... part of our Hardware Development group. The Sr. Digital Design Engineer needs to be able to...tools to check the functionalities of the designs in RTL and gate level. Collaborate with other… more
    BrainChip, Inc. (09/11/25)
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  • Senior ASIC Engineer , IP Design

    Google (Mountain View, CA)
    …related field, or equivalent practical experience. + 8 years of experience with RTL design using Verilog/System Verilog and microarchitecture. + Experience with ... Senior ASIC Engineer , IP Design , Silicon _corporate_fare_ Google...estimation, timing closure, synthesis. + Experience with methodologies for RTL quality checks (eg, Lint, CDC, RDC). **About the… more
    Google (11/06/25)
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