• Principal or Senior Principal Digital Verification…

    Northrop Grumman (San Diego, CA)
    …tools; 3 years with an MS degree; 0 years with PhD. + Experience in RTL design and verification methodologies for wireless systems + FPGA development ... tools; 7 years with an MS degree; 4 years with PhD. + Experience in RTL design and verification methodologies for wireless systems + FPGA development… more
    Northrop Grumman (04/18/25)
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  • Digital Design Engineer

    Meta (San Diego, CA)
    …SoCs that accelerate machine-learning and compute-vision workloads. **Required Skills:** Digital Design Engineer Responsibilities: 1. Contribute to ASIC digital ... Qualifications: 8. 3+ years of experience as a Hardware Design Engineer for production silicon shipped in...production silicon shipped in volume 9. Experience in digital design uArchitecture and RTL coding 10. Experience… more
    Meta (05/01/25)
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  • Design Verification Engineer

    SpaceX (Sunnyvale, CA)
    …analyzing results + Experience with scripting languages, eg Python for automation + RTL design , chip bring-up, and post-silicon validation experience + Ability ... Design Verification Engineer (Silicon Engineering) Sunnyvale,...Starlink network. RESPONSIBILITIES: + Responsible for digital ASIC and/or FPGA verification at block and system level + Write… more
    SpaceX (04/15/25)
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  • Camera Emulation Engineer

    Qualcomm (San Diego, CA)
    …programming skills and/or Perl/Python scripting skills + ASIC Logic / RTL Design experience & background with experience in FPGA and Emulation model ... smarter, connected future for all. As a Qualcomm Camera Engineer you will work on ideas that touch our...the world of Imaging. + Deliver emulation models from RTL using industry standard emulation technology + Plans simulation… more
    Qualcomm (02/06/25)
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  • IC DV Emulation Principal Application…

    Cadence Design Systems, Inc. (San Jose, CA)
    … prototyping Experience with multiple clock domains and asynchronous interfaces Knowledge of the FPGA development process & tool flow from RTL to bitstream for ... semiconductor and system companies to deploy Cadence's market leading emulation and FPGA prototyping platforms, Palladium and Protium. In this customer facing role… more
    Cadence Design Systems, Inc. (05/05/25)
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  • ASIC Physical Design Engineer

    Amazon (Cupertino, CA)
    …analysis, and physical verification * Write Tcl or PERL scripts to improve physical design flows and methods * Collaborate with RTL , DFT designers to ensure ... Annapurna Labs we are at the forefront of hardware co- design not just in Amazon Web Services (AWS) but...use for accelerated computing: either Machine Learning acceleration, or FPGA acceleration. We get our hands dirty, from creating… more
    Amazon (04/04/25)
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  • VLSI Design Engineer for Server…

    Qualcomm (San Diego, CA)
    …bright ASIC engineers with excellent analytical and technical skills. Besides solid ASIC and/or FPGA design experience, this professional need to be a great team ... is a great opportunity to join a fast-paced SoC team responsible for RTL Design , flows and methodology for high performance ASICs in the latest process nodes… more
    Qualcomm (02/14/25)
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  • Design Verification (DV) Engineer

    Cisco (San Jose, CA)
    …ASICs being developed in the industry. Your Impact You will work with front-end RTL Design and Verification teams and Architects to understand chip architecture ... hardware platforms for Cisco's core Switching, Routing, and Wireless products. We design the networking hardware for Enterprises and Service Providers of various… more
    Cisco (04/28/25)
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  • Staff Digital Verification Engineer

    Northrop Grumman (San Diego, CA)
    …tools; 12 years with an MS degree; 9 years with PhD. + Experience in RTL design and verification methodologies for wireless systems + FPGA development ... a career engineering what's possible as a Digital Verification Engineer in San Diego, CA. **What You'll Get to...systems aboard the world's most advanced platforms. We bring design to life in our San Diego labs and… more
    Northrop Grumman (04/18/25)
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  • SOC Debug Engineer

    Qualcomm (San Diego, CA)
    …software engineers, and customers to solve the toughest issues spanning board design , SoC RTL , microcontroller firmware, OS/software, and process variation. We ... an experienced candidate for the position of SoC Debug Engineer . **Key Responsibilities** In this role, the candidate will...RTL , FW, and SW levels in both Pre-Si ( FPGA prototyping) and Post-Si (ASIC) phases 2. Develop, implement,… more
    Qualcomm (02/08/25)
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