- Meta (Sunnyvale, CA)
- …must be completed prior to joining Meta 8. 2+ years of experience as a Digital Design Engineer 9. Experience in RTL coding, synthesis and/or SoC Integration ... **Summary:** As a Digital Design Engineer at Meta Reality Labs,...Responsible for top-level or block level uArchitecture definition and RTL implementation 2. Contribute to chip-level integration, verification plan… more
- Amazon (Sunnyvale, CA)
- …that is powering the latest generation of Echo devices is looking for a Senior Design Verification Engineer to continue to innovate on behalf of our customers. ... and the full chip. You will participate in the design verification and bring-up of the chip and subsystems...in the lab bring-up of these blocks either in FPGA , emulation, or silicon by potentially writing test scripts,… more
- SpaceX (Irvine, CA)
- Sr. ASIC Design Engineer (Silicon Engineering) Irvine, CA Apply SpaceX was founded under the belief that a future where humanity is out exploring the stars is ... goal of enabling human life on Mars. SR. ASIC DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're...requirements and system limitations + Define micro-architecture, implement the RTL in Verilog/System Verilog, integrate that in top level… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …subsystem verification and/or performance analysis* Strong knowledge of ASIC flow, RTL design in Verilog, System Verilog and FPGA design * Knowledge of ... an impact on the world of technology. Senior Applications Engineer - DDR Design IPJob Location: San...opportunities* Run Verilog simulations to enable IP benchmarking* Run RTL synthesis for area and timing analysis* Present IP… more
- Meta (San Diego, CA)
- **Summary:** As a Digital Design Engineer at Meta Reality Labs, you will work with a world-class group of researchers and engineers, and use your digital ... our industry leading virtual and augmented reality systems. **Required Skills:** Digital Design Engineer Responsibilities: 1. Responsible for top-level or block… more
- Google (Mountain View, CA)
- ASIC Design Verification Engineer , Devices and Services _corporate_fare_ Google _place_ Mountain View, CA, USA **Mid** Experience driving progress, solving ... unparalleled performance, efficiency, and integration. As an Application-Specific Integrated Circuit (ASIC) Design Verification Engineer , you will be part of a… more
- Google (Mountain View, CA)
- Staff ASIC Design Verification Engineer , Platforms and Devices _corporate_fare_ Google _place_ Mountain View, CA, USA **Advanced** Experience owning outcomes and ... to product release. + Experience strategizing and verifying digital logic at RTL and GLS level using SystemVerilog or C/C++ or Universal Verification Methodology… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …on memory subsystem verification and/or performance analysis . Knowledge of System Verilog and FPGA design . Knowledge of AXI, DFI and MIPI protocols . Working ... Join the High-Performance Culture at Cadence. As a Lead Technical Presales Engineer , you will use your knowledge of different memory interface standards to… more
- Amazon (San Diego, CA)
- …a state of the art verification environment to facilitate testing of the RTL against reference Matlab/C models . Develop detailed test plans and write tests, ... to execute on embedded CPU . Develop tests for FPGA and emulation platforms . Run formal verification of...blocks to ensure functional correctness . Work with the design and communication systems team and participate in system… more
- Microsoft Corporation (San Jose, CA)
- …testing, and deploying networking acceleration on Azure, and the largest deployment of Field-Programmable Gate Array ( FPGA ) SmartNICs (Azure Boost) ... This is a unique opportunity for a Senior Verification Engineer to see Register-Transfer Level ( RTL ) code...functional scenarios in discussions with the software and hardware design teams. * Execute the test plan by adding… more