• ASIC Design Engineer - Design & Timing Constraints

    Cisco (San Jose, CA)
    …+ Option to also do block level RTL design or block or top-level IP integration + Helping develop efficient methodology to promote block level SDCs to fullchip, and ... + Experience with constraint analyzer tools such as TCM (Timing Constraint Manager from Synopsys) and CCD (Conformal Constraint Designer from Cadence) + Experience… more
    Cisco (06/25/25)
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