- NVIDIA (Santa Clara, CA)
- …experience) + 5+ years of verification experience + Exposure to Computer Architecture, ASIC design and verification methodology is required + Strong ability with ... NVIDIA is seeking best-in-class ASIC Verification Engineers to verify the world's leading...working across many NVIDIA teams from software, to architecture, design , methodology, and more. The GPU is used in… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior ASIC Verification Engineer ! NVIDIA is seeking an outstanding engineer to verify the design and implementation of the ... performance of PCIe and CXL designs + Understand the design , define the verification scope, develop the verification infrastructure,...the verification infrastructure, and verify the correctness of the design What we need to see: + BS or… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior ASIC Engineer in the area of DFX ATPG flows and methodologies. Do you like to think creatively and enjoy solving challenges ... from you! What you'll be doing: + Support the deployment of advanced Design -For-Test (DFT) and Automatic Test Pattern Generation (ATPG) solutions + Work with… more
- NVIDIA (Santa Clara, CA)
- … tradeoffs and methodology on next generation CMOS technology. We are looking for a Senior ASIC Timing Engineer to join our dynamic and growing team! ... Engineering or equivalent experience. + 8+ years experience in Physical design /Timing. + Experience in full-chip/sub-chip Static Timing Analysis (STA), timing… more
- NVIDIA (Santa Clara, CA)
- …years of EDA tool development in the verification field + Hands on experience with ASIC design and verification + Good with C++ and other programming languages ... stand out from the crowd: + Good understanding of Design for Testing including Scan/ATPG/JTAG. + Strong English communication....working for us. Are you a creative and autonomous engineer who loves a challenge? Come join our GPU… more
- NVIDIA (Santa Clara, CA)
- …5+ years' experience or MS (or equivalent experience) with 3+ years' experience in ASIC Design and Timing + Hands-on experience in STA tools, ECO implementation, ... cross-functional teams. + Strong understanding of timing and physical design fundamentals Ways to stand out from the crowd:...critical paths. + Background and expertise in high frequency design closure at subsystem level. + Ability to develop… more
- NVIDIA (Santa Clara, CA)
- …multifaceted, multi-functional team at NVIDIA. We sit at the crossroads of design , architecture, marketing, and productization. Our involvement begins at the arch ... and implementation plan across multiple business units, translate hardware features design requirements to silicon speed characterization needs and test requirements… more
- Amazon (Sunnyvale, CA)
- …provide low-latency, high-speed broadband connectivity. Come work at Amazon! The Role: As Senior CAD Engineer you will be responsible for installing and ... maintaining EDA tools and flows for project Kuiper's digital design teams. This is an opportunity to define the...teams. This is an opportunity to define the digital design environment and deploy methodology of a new project… more
- Microsoft Corporation (Santa Clara, CA)
- …compared to CPU-based alternatives Microsoft DPU team in Santa Clara is looking for a Senior Design For Test Engineer to help develop their next generation ... hardware expertise to create a highly programmable and high-performance ASIC with the capability to efficiently handle large data...experience. + 2+ years of industry experience as a Design For Test (DFT) engineer . + Hands… more
- Silvus Technologies (Los Angeles, CA)
- …a fulfilling career. THE OPPORTUNITY Silvus is seeking a full-time **_Senior FPGA Design Engineer_** reporting to the _Director of FPGA Engineering_ on the _FPGA ... and development process from concept to field deployment. FPGA Design Engineers are responsible for the efficient implementation of...skill. + Experience with communication systems on FPGA or ASIC designs. **COMPENSATION** _The pay range is NOT a… more