- NVIDIA (Santa Clara, CA)
- …to amplify human inventiveness and intelligence. We are now looking for a motivated Senior ASIC Physical Design Engineer , Netlisting to join our dynamic ... checks, etc. + Help in all aspects of physical design, such as driving timing convergence, timing constraints generation and management, and ECO generation and… more
- NVIDIA (Santa Clara, CA)
- We are looking for a Senior ASIC Design Engineer to join our Switch Silicon team. As a Design Engineer at NVIDIA, you'll join a group of hardworking ... micro-architecture, implement in RTL, and deliver a fully verified, synthesis/ timing clean design. + Collaborate with architects, verification engineers, formal… more
- NVIDIA (Santa Clara, CA)
- …Make the choice to join us today. The clocks group is looking for a top-notch ASIC engineer to join the team. The Team is responsible for crafting all aspects ... evaluating trade-offs across DFx, Physical Implementation, Power Optimization and Ease of timing closure to innovate and implement new Clocking topologies in RTL. +… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a motivated Senior ASIC Design Engineer to join our dynamic and growing team in our Circuit Solutions Group! NVIDIA has continuously ... + Strong familiarity and experience with all stages of ASIC design flow including front end design and verification,...flow including front end design and verification, DFT, and timing analysis + Strong team player with outstanding interpersonal… more
- SpaceX (Sunnyvale, CA)
- …to work extended hours and weekends as needed COMPENSATION & BENEFITS: Pay range: ASIC Design Engineer / Senior : $210,000.00 - $280,000.00/per year Your actual ... Principal ASIC Design Engineer (Silicon Engineering) Sunnyvale,...that in top level and deliver the fully verified, synthesis/ timing clean design + Work closely with verification team… more
- Palo Alto Networks (Santa Clara, CA)
- …and the kind of precision that drives great outcomes. **Your Career** Join our ASIC team and help deliver the digital logic that powers our next-generation firewall ... and add design-for-debug features. + **Partner** with physical-design teams: review synthesis/ timing reports, rewrite RTL to close critical paths, and consult on… more
- Amazon (Sunnyvale, CA)
- …Fire tablets, Fire TV and Amazon Echo. What will you help us create? The Role: As a Senior ASIC Design Engineer , you will be part of an advanced design and ... in design methodologies and EDA tools - Experience working with Synthesis, timing closure, and design constraints Preferred Qualifications - Experience with ARM and… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior ASIC Design Engineer - DFX NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 ... architects, platform, and software teams. + Partner with design, verification, synthesis, timing , and backend teams to ensure cohesive integration. + Create and… more
- NVIDIA (Santa Clara, CA)
- …on-chip interconnect network and last-level caches, working on implementation, synthesis and timing closure while collaborating closely with the logic design team on ... Logic design and Physical design teams responsible for achieving timing , area, performance and power goals of the unit....expertise is preferred as is a deep understanding of ASIC design flow including RTL design and verification, DFT,… more
- Amazon (Cupertino, CA)
- …scale and rapid integration of emergent technologies. We're looking for an ASIC Design Eengineer to help us trail-blaze new technologies and architectures, while ... signal routing - As a key member of the ASIC design team, you will implement and deliver high...requirements. - Develop micro-architecture, implement SystemVerilog RTL, and deliver synthesis/ timing clean design with constraints. - Perform lint and… more