- SpaceX (Sunnyvale, CA)
- Sr. SOC/ ASIC DFT Engineer (Silicon Engineering) Sunnyvale, CA Apply SpaceX was founded under the belief that a future where humanity is out exploring the stars ... ultimate goal of enabling human life on Mars. SR. SOC/ ASIC DFT ENGINEER (SILICON ENGINEERING) At SpaceX...as needed COMPENSATION AND BENEFITS: Pay range: Physical Design Engineer / Senior : $170,000.00 - $230,000.00/per year Your actual… more
- SpaceX (Sunnyvale, CA)
- Sr. SOC/ ASIC Physical Design Methodology/CAD Engineer (Silicon Engineering) Sunnyvale, CA Apply SpaceX was founded under the belief that a future where humanity ... possible, with the ultimate goal of enabling human life on Mars. SR. SOC/ ASIC PHYSICAL DESIGN METHODOLOGY/CAD ENGINEER (SILICON ENGINEERING) At SpaceX we're… more
- Amazon (Cupertino, CA)
- …scale and rapid integration of emergent technologies. We're looking for an ASIC Design Eengineer to help us trail-blaze new technologies and architectures, while ... signal routing - As a key member of the ASIC design team, you will implement and deliver high...requirements. - Develop micro-architecture, implement SystemVerilog RTL, and deliver synthesis/ timing clean design with constraints. - Perform lint and… more
- Broadcom (Irvine, CA)
- …Account, please Sign-In before you apply.** **Job Description:** Looking for a design engineer to work on challenging high speed design of complex modules for ... + Familiarity with digital chip design concepts, such as clocking, timing , pipelines, and performance vs area/power tradeoffs. **Additional Job Description:**… more
- Amazon (San Diego, CA)
- …in silicon from system specification to chip specification to RTL to optimizing timing / power to chip level validation . Develop solutions optimizing customer ... constructed using UVM, System C and DPI-C . Ensure that the block meets DFT, timing and power targets by working closely with the implementation team . Learn about… more
- NVIDIA (Santa Clara, CA)
- …work, to amplify human inventiveness and intelligence. We are seeking an innovative Senior Timing Methodology Engineer to help drive sign-off strategies ... in Electrical or Computer Engineering with 3 years' experience in ASIC Design and Timing . + Good understanding of modeling circuits for sign-off + Good… more
- NVIDIA (Santa Clara, CA)
- …ideally for EDA, semiconductor, or complex data domains + .Strong background in VLSI/ ASIC design - with deep understanding of timing , constraints, STA, or ... is our life's work, to amplify human inventiveness and intelligence. NVIDIA's ASIC -PD Methodology organization is driving the next generation of AI-assisted … more
- NVIDIA (Santa Clara, CA)
- …work, to amplify human inventiveness and intelligence. We are seeking an innovative Senior Timing Methodology Engineer to help drive sign-off strategies ... in Electrical or Computer Engineering with 5+ years experience in ASIC Design and Timing . + Proven understanding of circuit design and spice simulations.… more
- NVIDIA (Santa Clara, CA)
- …NICs, Switches on standard FPGA prototyping platforms. We are now looking for a Senior Systems Prototyping Engineer to join our Emulation team onsite in Santa ... Are you passionate about DGX system connecting multiple ASIC chips together and FPGA prototyping? Are you...and route. + Improve performance of the prototype, analyze timing and generate bit streams. + Bring up the… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …who want to make an impact on the world of technology. We are looking for SoC/ ASIC Digital Design Engineer with experience in Design for Test (DFT). An intimate ... preferred. + Prior 5-15 years of professional experience in SoC/ ASIC Digital Design with focus on Design for Test...of JTAG 1149.1/6, IEEE1500 and IEEE1687 + Knowledge of timing analysis and equivalency checks would be added bonus… more