- NVIDIA (Santa Clara, CA)
- …NICs, Switches on standard FPGA prototyping platforms. We are now looking for a Senior Systems Prototyping Engineer to join our Emulation team onsite in Santa ... Are you passionate about DGX system connecting multiple ASIC chips together and FPGA prototyping? Are you...and route. + Improve performance of the prototype, analyze timing and generate bit streams. + Bring up the… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Logic Design Engineer with Physical Design background! As a member of our CPU Logic Design Team, you will be responsible for the design of ... working closely with the physical design team on implementation, synthesis and timing closure as well as working on micro-architectural definition and RTL… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior Signal & Power Integrity Engineer ! NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 ... work in dynamic cross-functional role to optimize package, PCB, ASIC , mixed signal circuit What we need to see:...time domain simulations. + Background with a system level timing or loss budget including silicon, package and board… more
- Cisco (San Jose, CA)
- Senior DFx/RTL Engineer Apply (https://jobs.cisco.com/jobs/Login?projectId=1447271) + Location:San Jose, California, US + Area of InterestEngineer - Hardware + ... **Your Impact:** You will be in the Silicon One development organization as an ASIC Implementation Technical Lead in San Jose, CA with a primary focus on… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior Signal & Power Integrity Engineer ! NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 ... in a dynamic cross-functional role to optimize package, PCB, ASIC , mixed signal circuit. What we need to see:...such as Ansys2D. + Familiarity with a system level timing or loss budget including silicon, package and board… more
- Silvus Technologies (Los Angeles, CA)
- …career._ THE OPPORTUNITY Silvus is seeking a **_Senior FPGA / RTL Design Engineer - Signal Processing_** who will report to the _Director of FPGA Engineering_ ... coding, simulation, and test bench development. + FPGA synthesis and timing closure. + Hardware verification and troubleshooting; familiarity with logic analyzers.… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …and innovators who want to make an impact on the world of technology. Senior Applications Engineer - DDR Design IPJob Location: San Jose, CAJob DescriptionThe ... Join the High-Performance Culture at Cadence.As a Technical Presales Engineer , you will support the technical presales of DDR...simulations, synthesis and publications. As you grow into more senior roles, you will use your knowledge of different… more
- Silvus Technologies (Irvine, CA)
- …coding, simulation, and test bench development. + FPGA synthesis and timing closure. + Hardware verification and troubleshooting; familiarity with logic analyzers. ... (MSEE). + Basic MATLAB skill. + Experience with communication systems on FPGA or ASIC designs. **COMPENSATION** _The pay range is NOT a guarantee. It is based on… more
- NVIDIA (Santa Clara, CA)
- …looking for a Senior Design for Debug (DFD) Architect and Methodology Engineer ! NVIDIA is seeking a DFD Architect to implement hardware and software solutions to ... logic analyzers and/or other silicon visibility tools. + Great understanding of ASIC design flow including RTL design, verification, logic synthesis, timing … more
- NVIDIA (Santa Clara, CA)
- …you can make a lasting impact on the world! We are currently looking for a Senior Methodology Engineer to develop and support our CAD tooling in our Circuit ... of experience in VLSI CAD flows and methodology + Timing closure and STA tool experience required + Good...out from the crowd: + Previous work in VLSI, ASIC , or EDA is a definite plus + Experience… more