- NVIDIA (Santa Clara, CA)
- …complex challenges across diverse industries. NVIDIA Silicon Solutions Group is seeking a versatile engineer to be part of the HW ArchDev team. The SSG team is ... and power based on roadmap. + Work closely with architecture, ASIC , board/platform design, software/firmware, marketing, and other cross-functional teams to drive… more
- NVIDIA (Santa Clara, CA)
- …amplify human inventiveness and intelligence. NVIDIA Silicon Solutions Group seeks a versatile engineer to join a Silicon HW team. You will interpret product goals, ... working with and optimizing Data Center systems. + Experience with ASIC power-saving features, system-level power-saving features, and experience optimizing products… more
- quadric.io, Inc (Burlingame, CA)
- …to get in on the ground floor of a revolutionary new processor architecture. As a senior member of our chip design team, you will contribute to all stages of the ... + Own Power, Performance & Area (PPA) optimization + Contribute to timing closure through full product cycle (front end, back-end, tapeout) Requirements: +… more
- NVIDIA (Santa Clara, CA)
- …fundamentals, knowledgeable in digital design, computer architecture, power analysis, timing analysis, fault analysis, sampling, statistics, and scripting + Hands-on ... debug and lab tools (oscilloscopes, multimeters, logic analyzers). + Experience with ASIC power saving features and methods + Deep understanding of firmware/driver… more
- Broadcom (San Jose, CA)
- …Account, please Sign-In before you apply.** **Job Description:** Broadcom is looking for a senior level STA engineer . In this highly visible role, you will be ... data center connectivity products. Responsibilities Include: + Develop and validate timing constraints for intricate SoC designs. + Perform static timing… more
- Silvus Technologies (Irvine, CA)
- …career._ THE OPPORTUNITY Silvus is seeking a full-time Principal FPGA / RTL Design Engineer who will report to the Senior Engineering Director for Irvine and ... addressing challenging real-world communication needs. The Principal FPGA / RTL Design Engineer position will be based at Silvus' Irvine CA engineering facility… more
- Broadcom (San Jose, CA)
- …Account, please Sign-In before you apply.** **Job Description:** **Broadcom is looking for a senior level ASIC physical design engineer . In this highly ... issues at the chip and block level.** + **Experience with CDC, static timing analysis methodologies and relevant tools.** + **Exposure to SDF annotated simulations… more
- L3Harris (Anaheim, CA)
- …providing critical technology advancements in the areas of GPS/Position Navigation and Timing , and Range and Test Solutions. We offer competitive benefits, an ... group of professionals. Job Description: As a Lead Electrical Engineer , the candidate must have experience with L band...and flow down applicable requirements to other groups (software, ASIC , & test) so that they can contribute to… more
- Amazon (Cupertino, CA)
- …and validation. A day in the life A day in the life of an ASIC Engineer on the AWS Organization team focuses on operational excellence, constructively ... generation ML Chips, Cards and server integration. As a senior member of our platform development team, you will...within AWS datacenter's world leading technology. The HBM lead Engineer will need to independently work with vendors, understand… more
- Amazon (Sunnyvale, CA)
- …Edge that is powering the latest generation of Echo devices is looking for a Senior SoC Design-STA Engineer to continue to innovate on behalf of our customers. ... for STA, Crosstalk Delay and Crosstalk Noise analysis for digital ASIC /SoCs. * Full chip timing constraints development, full chip / Sub-System STA and Signoff… more
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