• Senior E/E & Semiconductor Engineer…

    Capgemini (San Jose, CA)
    …and optimize data structures and algorithms to solve complex problems. + Support ASIC design and verification processes. + Develop and manage projects in ... considering:** We are seeking a highly skilled Python Infrastructure Engineer with a strong foundation in Python programming, data...and algorithms! + ASIC Flow: Knowledge of ASIC design and verification processes. + Linux… more
    Capgemini (09/20/25)
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  • Digital Verification Engineer

    Broadcom (San Jose, CA)
    …Account, please Sign-In before you apply.** **Job Description:** Broadcom is looking for a senior level Digital Design Verification engineer . In this highly ... visible role you will be working on ASIC for data center connectivity applications. Qualifications include: +...Engineering with 6+ years of experience in digital design verification + Hands on experience in SV UVM, SV… more
    Broadcom (07/11/25)
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  • Senior Systems Prototyping Engineer

    NVIDIA (Santa Clara, CA)
    …NICs, Switches on standard FPGA prototyping platforms. We are now looking for a Senior Systems Prototyping Engineer to join our Emulation team onsite in Santa ... Protocompiler or Synplify Premier and Xilinx Vivado + Exposure to ASIC design and verification tools (VCS or equivalent, Verdi, GDB). + Knowledge of Verilog,… more
    NVIDIA (09/17/25)
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  • Senior System SW Engineer , System…

    Palo Alto Networks (Santa Clara, CA)
    …Processor Tool Chain Development - Assembler, Debugger, Simulator + Infrastructure to support ASIC team development and verification + ASIC microcode and ... In-depth knowledge of networking equipment & architectures - system hardware, CPUs, ASIC etc. + Experienced in networking protocols - mobile, routing, transport… more
    Palo Alto Networks (09/19/25)
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  • Senior Emulation Engineer

    Capgemini (Sunnyvale, CA)
    **Position: Emulation Validation/ Verification Engineer ** **Location: onsite bay area preferred; any Capgemini office location also will be considered; Hybrid** ... **About the job you're considering** Experienced Emulation Engineer responsible for validating and debugging complex ...bugs. **Your role** * Execute DV testcases: Run functional verification tests on the ZeBu emulation platform to identify… more
    Capgemini (08/23/25)
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  • Senior DFx/RTL Engineer

    Cisco (San Jose, CA)
    Senior DFx/RTL Engineer Apply (https://jobs.cisco.com/jobs/Login?projectId=1447271) + Location:San Jose, California, US + Area of InterestEngineer - Hardware + ... be in the Silicon One development organization as an ASIC Implementation Technical Lead in San Jose, CA with...coordinated in the RTL. + Work closely with the design/design- verification and PD teams to enable the integration and… more
    Cisco (09/24/25)
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  • Electrical Engineer (Associate, Mid-Level,…

    The Boeing Company (El Segundo, CA)
    …Analysis * Power Supply * Electronics Packaging * ASIC FPGA Development and Verification * Electrical Design System Engineer * RF Microwave Engineer * ... has exciting opportunities for **Electrical Engineers (Associate, Mid-Level, or Senior )** to join us as part of our teams...for Mid-Level: $104,550 - $141,450 Summary pay range for Senior : $126,650 - $171,350 Applications for this position will… more
    The Boeing Company (09/07/25)
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  • Senior FPGA Design Engineer

    Silvus Technologies (Irvine, CA)
    …test bench development. + FPGA synthesis and timing closure. + Hardware verification and troubleshooting; familiarity with logic analyzers. + Provide support to the ... (MSEE). + Basic MATLAB skill. + Experience with communication systems on FPGA or ASIC designs. **COMPENSATION** _The pay range is NOT a guarantee. It is based on… more
    Silvus Technologies (08/18/25)
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  • Senior Design for Debug Architect…

    NVIDIA (Santa Clara, CA)
    …looking for a Senior Design for Debug (DFD) Architect and Methodology Engineer ! NVIDIA is seeking a DFD Architect to implement hardware and software solutions to ... and/or other silicon visibility tools. + Great understanding of ASIC design flow including RTL design, verification ,...of ASIC design flow including RTL design, verification , logic synthesis, timing analysis and bringup. + Strong… more
    NVIDIA (09/10/25)
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  • Senior Mask Design Engineer…

    NVIDIA (Santa Clara, CA)
    …Engineer ? If yes, We would love to hear from you! We are looking for a Senior Mask Layout Design Engineer , someone who is excited to join a growing and ... sub-micron CMOS technologies using Cadence tools. + You'll work multi-functional with ASIC and mixed-signal engineers to customize designs for integration in VLSI… more
    NVIDIA (08/28/25)
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