• Senior DFT Engineer

    NVIDIA (Santa Clara, CA)
    …Make the choice to join us today. NVIDIA's DFX team is looking for an exceptional DFT Engineer to help shape the future of compute. As stewards of the entire ... teams to drive scalable, automated solutions. + Co-architect novel DFT strategies alongside VLSI and Product Engineering teams to...field + 5+ years of hands-on experience in Design-For-Test ( DFT ) + Deep knowledge of DFT tools,… more
    NVIDIA (06/17/25)
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  • Senior DFT Methodology…

    NVIDIA (Santa Clara, CA)
    …experience) with 5+, MSEE with 3+, or PhD with 2+ years of experience in DFT , system architecture, or RTL design. + Understanding of fundamental DFT topics, such ... of MBIST and IOBIST fundamentals. + Experience in architecting DFT access mechanisms in 3D stacked and dielet/chiplet based...are growing fast. If you're a creative and autonomous engineer with real passion for technology, we want to… more
    NVIDIA (07/01/25)
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  • Senior DFx/RTL Engineer

    Cisco (San Jose, CA)
    Senior DFx/RTL Engineer Apply (https://jobs.cisco.com/jobs/Login?projectId=1447271) + Location:San Jose, California, US + Area of InterestEngineer - Hardware + ... teams, backend physical design teams to understand chip architecture and drive DFT requirements early in the design cycle. **Key Responsibilities:** + Responsible… more
    Cisco (07/22/25)
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  • Senior Product Test Engineer

    Cisco (San Jose, CA)
    Senior Product Test Engineer Apply (https://jobs.cisco.com/jobs/Login?projectId=1444763) + Location:San Jose, California, US + Area of InterestSupply Chain + ... in Silicon Operations, and with Cisco Systems NPI teams. Collaborate with DFT , Reliability, Quality, Failure Analysis and Manufacturing teams to resolve silicon… more
    Cisco (07/11/25)
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  • Senior ASIC Timing Engineer

    NVIDIA (Santa Clara, CA)
    …design tradeoffs and methodology on next generation CMOS technology. We are looking for a Senior ASIC Timing Engineer to join our dynamic and growing team! If ... frequency and power/area/congestions/yield/etc. + Work on all aspects of DFT /Test timing such as timing constraints, timing analysis, timing...to stand out from the crowd: + Experience with DFT timing closure for various modes eg scan shift,… more
    NVIDIA (06/10/25)
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  • Senior ASIC Synthesis Engineer

    NVIDIA (Santa Clara, CA)
    …design tradeoffs and methodology on next generation CMOS technology. We are looking for a Senior ASIC Synthesis Engineer to join our dynamic and growing team! If ... You'll Be doing: + As a Front-End ASIC Synthesis Engineer , you will own RTL synthesis and gate level...power/area optimization across multiple design blocks + Work with DFT and Verification teams to ensure functional and timing… more
    NVIDIA (07/01/25)
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  • Senior ASIC Design Engineer…

    NVIDIA (Santa Clara, CA)
    We are now looking for a motivated Senior ASIC Design Engineer to join our dynamic and growing team in our Circuit Solutions Group! NVIDIA has continuously ... + Work with front-end teams to overlook correctness of the design (Lint/NA/CDC/Synthesis/ DFT /LEC/STA) + Partner and work with back-end team until chip tape-out. +… more
    NVIDIA (08/27/25)
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  • Senior Hardware Design Engineer…

    General Motors (Mountain View, CA)
    …design and development of our vehicle displays hardware. In this role, the Senior Hardware Design Engineer - Display Development will be responsible for ... (DFM), design for assembly (DFA), and design for testing ( DFT ) + Drive the validation and testing of hardware...(DFM), design for assembly (DFA), and design for testing ( DFT ) + Excellent problem-solving, analytical, and communication skills. +… more
    General Motors (08/26/25)
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  • Senior ASIC Engineer - DFX

    NVIDIA (Santa Clara, CA)
    We are now looking for a Senior ASIC Engineer in the area of DFX ATPG flows and methodologies. Do you like to think creatively and enjoy solving challenges that ... be doing: + Support the deployment of advanced Design-For-Test ( DFT ) and Automatic Test Pattern Generation (ATPG) solutions +...to stand out from the crowd: + Knowledge of DFT including fault models, ATPG, fault simulation, and diagnosis… more
    NVIDIA (07/26/25)
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  • Senior Principal Test Engineer…

    Palo Alto Networks (Santa Clara, CA)
    …for the manufacturing capabilities to build our next-generation network firewalls. As a senior test engineer , you will be responsible for building advanced test ... for test coverage and serviceability with ICT and boundary scan + Drive DfT (Design for Testability) and test coverage analyses from early Prototype design stages… more
    Palo Alto Networks (07/05/25)
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