• Senior Signal Processing…

    Leidos (San Diego, CA)
    …to support EW programs in Arlington, VA or San Diego, CA. As a **LInC EW Senior Signal Processing Engineer ** , you will be responsible for research, design, ... and development of signal collection, processing and dissemination systems. Duties may include...and analyzing systems for the extraction of information from signal sensors. You will support the Division by achieving… more
    Leidos (07/03/25)
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  • Senior Signal Processing…

    Leidos (San Diego, CA)
    …Center (LInC) at Leidos (in Arlington, VA or San Diego, CA) currently has an opening for a ** Senior Signal Processing Engineer ** . As a **LInC EW Senior ... you will be responsible for research, design, and development of signal collection, processing and dissemination systems. Duties may include designing, developing,… more
    Leidos (06/25/25)
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  • Senior Signal and Power Integrity…

    NVIDIA (Santa Clara, CA)
    We are now looking for a Senior Signal & Power Integrity Engineer ! NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in ... What you'll be doing: + Work on crafting creative Signal Integrity solutions to complex system design problems. +...various system components in 3D EM tools. + System-level signal integrity simulations of high-speed NVlink 200Gbs+, USB-4, PCIe5,… more
    NVIDIA (07/11/25)
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  • Senior Signal and Power Integrity…

    NVIDIA (Santa Clara, CA)
    We are now looking for a Senior Signal & Power Integrity Engineer ! NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in ... What you'll be doing: + Work on crafting creative Signal Integrity solutions to complex system design problems. +...various system components in 3D EM tools. + System-level signal integrity simulations of high-speed NVlink 200Gbs+, USB-4, PCIe5,… more
    NVIDIA (06/10/25)
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  • Senior Signal and Power Integrity…

    NVIDIA (Santa Clara, CA)
    We are now looking for a Senior Signal & Power Integrity Engineer ! NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in ... help move the needle! What you'll be doing: + Work on crafting creative Signal Integrity solutions to complex system design problems + System-level signal more
    NVIDIA (07/23/25)
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  • Senior Signal and Power Integrity…

    NVIDIA (Santa Clara, CA)
    We are now looking for a Senior Signal & Power Integrity Engineer ! NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in ... design guide implementation, layout review, and post-layout analysis. + System-level signal integrity simulation of PCIE, LPDDR/DDR/GDDR, MIPI, HDMI, USB and other… more
    NVIDIA (06/10/25)
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  • Senior Mixed Signal Design…

    Capgemini (Santa Clara, CA)
    **About the job you're considering** We're looking for a collaborative Senior Mixed- Signal Design Verification Engineer to help shape the future of SoC ... using SystemVerilog and UVM for IPs and SoCs with embedded CPUs and mixed- signal interfaces. + Contribute to AMS and power-aware verification efforts across multiple… more
    Capgemini (07/19/25)
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  • Senior Mixed Signal Design…

    NVIDIA (Santa Clara, CA)
    We are looking for a Senior Mixed- Signal /Analog/IO Circuit Design Engineer - someone who is excited to join a rapidly growing team of creative circuit design ... to amplify human creativity and intelligence. What you'll be doing: + Mixed- Signal /Analog circuit design for High-Speed Memory I/O Interfaces + Solve challenges of… more
    NVIDIA (07/13/25)
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  • Senior Analog/mixed- signal IC…

    Cisco (San Jose, CA)
    Senior Analog/mixed- signal IC Design Engineer - Acacia Apply (https://jobs.cisco.com/jobs/Login?projectId=1443040) + Location:San Jose, California, US + ... number of applications are received. Acacia designs intelligent transceivers using advanced signal processing and photonic integration for the 100G, 400G and 1T bit… more
    Cisco (08/08/25)
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  • Senior Signal Integrity…

    Palo Alto Networks (Santa Clara, CA)
    …and verify module/package and PCB layout rules: perform pre- and post-route signal integrity analysis of ASIC and multi-chip-module designs + Model and analyze ... power delivery networks for ASIC/package/module and PCB + Create SI test plan for coverage of all serdes, memory, and external IO interfaces + Drive creation and implementation for required test infrastructure (tools, scripts, etc.) with external vendors and… more
    Palo Alto Networks (07/26/25)
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