• Lead Principal Electrical Design Engineer

    Micron Technology, Inc. (San Jose, CA)
    …and circuit simulation platforms like LTspice or PSpice. + Strong understanding of PCB layout, signal integrity (SI), and power integrity (PI). + Skilled ... tester equipment and interface/load boards. + Architect high-performance analog circuits, power supplies, and FPGA-based solutions. + Conduct design reviews and… more
    Micron Technology, Inc. (10/27/25)
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  • Software Engineer Embedded/Network Systems…

    Cisco (San Jose, CA)
    …principles and security protocols. + Experience with FPGA development. + Knowledge of signal and power integrity , and PCB design. **Why Cisco?** ... experience with hardware-software integration and low-level networking technologies that power Cisco's critical products. Discover the possibilities when deep… more
    Cisco (12/12/25)
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  • Senior Manager, Silicon Product and Test…

    Google (Sunnyvale, CA)
    …Build and track high performance IC test and characterization flows for PVT, signal and power integrity characterization, System correlation, and participate ... part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products… more
    Google (12/04/25)
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  • Semiconductor Packaging Technical Leader (Hybrid)

    Cisco (San Jose, CA)
    …understanding of package design and material selection for thermal performance and signal / power integrity . + Expertise in advanced problem-solving ... innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the...our impact is everywhere. We are Cisco, and our power starts with you. **Message to applicants applying to… more
    Cisco (12/03/25)
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  • Packaging Technical Leader

    Cisco (San Jose, CA)
    …Familiar with advanced substrate manufacturing processes and materials and their impact on signal and power integrity . * Experience in advanced ... innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the...our impact is everywhere. We are Cisco, and our power starts with you. **Message to applicants applying to… more
    Cisco (11/12/25)
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  • Sr. System Electrical Engineer, eero

    Amazon (San Francisco, CA)
    …requirements * Develop and review board schematics * Review and optimize board layouts for signal and power integrity * Perform bring-up of new board designs ... the design of high- and low-speed digital interfaces, DC-DC converters, and power distribution networks - Understanding of the system integration challenges posed by… more
    Amazon (12/10/25)
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  • Principal Silicon Validation Engineer

    Blue Cheetah Analog Design (Sunnyvale, CA)
    …and customer platforms. * PCB and package design experience * Fluent with industry standard signal and power integrity tools * Generate and maintain IBIS ... model generation for D2D products * Experience with Verilog, VHDL, or other hardware description languages Equal Opportunity: Qualified applicants will receive consideration for employment without regard to, and will not be discriminated against based on race,… more
    Blue Cheetah Analog Design (10/13/25)
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  • Design Engineering Director

    Cadence Design Systems, Inc. (San Jose, CA)
    …Schematic and layout level. Familiarity with peripheral chips, high speed interface design techniques, Signal and Power integrity checks / analysis and fixes ... needed to meet the performance requirements. + Experience in PCIe/UCIe LTSSM states / UCIe Interfaces / Ethernet standards is a plus. + Proven experience in developing lab automation scripts and test result analysis to debug and root cause silicon failures. +… more
    Cadence Design Systems, Inc. (10/07/25)
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  • Sr. Full Chip Physical Design Engineer (Silicon…

    SpaceX (Sunnyvale, CA)
    …sub-micron FinFET technology nodes (7nm and below) design problems and solutions (leakage power , signal integrity , etc.) multi-corner and multimode timing ... bump & RDL (redistribution layer) planning, hard IP integration, partitioning, power /ground grid generation, pin assignment, partition hardening, chip level clock,… more
    SpaceX (11/14/25)
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  • Senior Hardware SoC Architect

    NVIDIA (Santa Clara, CA)
    …knowledge at least one of: 1) PLLs, DLLs, etc, 2) clock-related signal integrity effects, or 3) platform power and reset sequencing + Automotive Functional ... and Reset Architecture Team. This position requires an interest in clocks, resets and power management for SOCs. It will also require a strong background in System… more
    NVIDIA (11/21/25)
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