• Semiconductor Packaging Technical Leader (Hybrid)

    Cisco (San Jose, CA)
    …understanding of package design and material selection for thermal performance and signal / power integrity . + Expertise in advanced problem-solving ... innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the...our impact is everywhere. We are Cisco, and our power starts with you. **Message to applicants applying to… more
    Cisco (12/03/25)
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  • Packaging Technical Leader

    Cisco (San Jose, CA)
    …Familiar with advanced substrate manufacturing processes and materials and their impact on signal and power integrity . * Experience in advanced ... innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the...our impact is everywhere. We are Cisco, and our power starts with you. **Message to applicants applying to… more
    Cisco (11/12/25)
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  • Sr. System Electrical Engineer, eero

    Amazon (San Francisco, CA)
    …requirements * Develop and review board schematics * Review and optimize board layouts for signal and power integrity * Perform bring-up of new board designs ... the design of high- and low-speed digital interfaces, DC-DC converters, and power distribution networks - Understanding of the system integration challenges posed by… more
    Amazon (12/10/25)
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  • Principal Silicon Validation Engineer

    Blue Cheetah Analog Design (Sunnyvale, CA)
    …and customer platforms. * PCB and package design experience * Fluent with industry standard signal and power integrity tools * Generate and maintain IBIS ... model generation for D2D products * Experience with Verilog, VHDL, or other hardware description languages Equal Opportunity: Qualified applicants will receive consideration for employment without regard to, and will not be discriminated against based on race,… more
    Blue Cheetah Analog Design (10/13/25)
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  • Design Engineering Director

    Cadence Design Systems, Inc. (San Jose, CA)
    …Schematic and layout level. Familiarity with peripheral chips, high speed interface design techniques, Signal and Power integrity checks / analysis and fixes ... needed to meet the performance requirements. + Experience in PCIe/UCIe LTSSM states / UCIe Interfaces / Ethernet standards is a plus. + Proven experience in developing lab automation scripts and test result analysis to debug and root cause silicon failures. +… more
    Cadence Design Systems, Inc. (10/07/25)
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  • Sr. Full Chip Physical Design Engineer (Silicon…

    SpaceX (Sunnyvale, CA)
    …sub-micron FinFET technology nodes (7nm and below) design problems and solutions (leakage power , signal integrity , etc.) multi-corner and multimode timing ... bump & RDL (redistribution layer) planning, hard IP integration, partitioning, power /ground grid generation, pin assignment, partition hardening, chip level clock,… more
    SpaceX (11/14/25)
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  • Senior Hardware SoC Architect

    NVIDIA (Santa Clara, CA)
    …knowledge at least one of: 1) PLLs, DLLs, etc, 2) clock-related signal integrity effects, or 3) platform power and reset sequencing + Automotive Functional ... and Reset Architecture Team. This position requires an interest in clocks, resets and power management for SOCs. It will also require a strong background in System… more
    NVIDIA (11/21/25)
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  • Display Electrical Engineer

    Meta (Sunnyvale, CA)
    …display panel, and display IC design 18. Knowledge of electrical signal integrity , simulations, display or system power delivery, and display electrical test ... system development 19. Experience with display electrical subsystem design/testing/validation/implementation 20. Experience with display module PCB/flex design, interfaces standards, display driver IC, and display backlight **Public Compensation:**… more
    Meta (11/26/25)
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  • Physical Design Engineer

    Broadcom (San Jose, CA)
    …Expertise in Cadence Innovus/Atop physical design tools - Experience on Calibre LVS/DRC - Low power , signal integrity experience - Work closely with RTL & ... DFT designers - Strong TCL/Python scripting knowledge required, Perl is a plus. - Good debug skill and be able to work around issues - Tape out experience - must be a good team player **Additional Job Description:** **Compensation and Benefits** The annual… more
    Broadcom (11/19/25)
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  • Hardware Systems Engineering Technical Lead

    Cisco (San Jose, CA)
    …designing systems with DDR4/DDR5 DIMMs * Experience with tackling signal integrity issues and board mounted power design and distribution techniques * ... series routers to deliver the best quality and best power efficiency using groundbreaking Serdes technology at the highest...with peer teams such as: Manufacturing, Software, Mechanical, or Signal Integrity * Expertise in Board Design… more
    Cisco (11/26/25)
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