• Sr. Silicon and Package Reliability…

    SpaceX (Hawthorne, CA)
    …(EEE) components and systems. This engineer ensures the reliability of our silicon and packaging products, from design to manufacturing, including ... Sr. Silicon and Package Reliability Engineer (Starshield)...Engineer plays a critical role in supporting the design engineering community to produce higher reliability Electrical, Electronic,… more
    SpaceX (01/01/26)
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  • SoC Silicon Top-Level Floorplan…

    Google (Sunnyvale, CA)
    SoC Silicon Top-Level Floorplan Engineer _corporate_fare_ Google _place_ Sunnyvale, CA, USA **Advanced** Experience owning outcomes and decision making, solving ... field, or equivalent practical experience. + 10 years of experience in physical design (eg, with a focus on floorplanning, integration, or top-level chip assembly).… more
    Google (12/20/25)
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  • Head of Silicon Package Reliability

    Google (Mountain View, CA)
    …package board interactions. + 10 years of experience managing a team across multiple silicon and packaging quality and reliability domains. + 6 years of ... in a reliability lead role. + Experience in modeling and reliability statistics for silicon , interconnects and packaging failure modes. **About the job** As a… more
    Google (12/05/25)
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  • Technical Program Manager, Custom Silicon

    Google (Mountain View, CA)
    …+ 8 years of experience as a Semiconductor Process, Yield, or Packaging Engineer . + Experience leading cross-functional teams, technical leadership, and ... Technical Program Manager, Custom Silicon Operations _corporate_fare_ Google _place_ Mountain View, CA,...of experience in Semiconductor Manufacturing (including wafer processing or packaging processing) and testing. + Experience with SoC and… more
    Google (12/11/25)
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  • Packaging Engineer

    Texas Instruments (Santa Clara, CA)
    …SC Packaging organization. **Responsibilities may include:** + To define, design , develop and scale to volume production high voltage (200-3300V) packages and ... world. Love your job.** As a member of our Packaging team, you'll have the chance to interact with...rapid time-to market for new products. **Why TI?** + Engineer your future. We empower our employees to truly… more
    Texas Instruments (12/26/25)
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  • Photonic Packaging Engineer

    Cisco (Carlsbad, CA)
    …working out of our Carlsbad, CA office location. **Meet the Team** As a Photonic Packaging Engineer , you will play a key role in developing/supporting the next ... generation packaging platform for Cisco's Silicon Photonics Integrated...developing critical optical components, processes, and tools. **Your Impact** Design , Develop and Support + Provide engineering support for… more
    Cisco (12/16/25)
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  • Sr Hardware Test and Packaging

    Cisco (Carlsbad, CA)
    …of our Carlsbad, CA office location. **Meet the Team** As Hardware Test & Packaging Engineer , you will help develop and support Cisco's next generation component ... and packaging platform for Cisco's Silicon Photonics Integrated...high-volume, automated optical assembly and test processes. **Your Impact** Design , Develop and Support + Work as part of… more
    Cisco (12/16/25)
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  • Senior Engineer , Front End Computer Aided…

    Microsoft Corporation (Mountain View, CA)
    …and software for our design engineers so that they can deliver cutting-edge silicon solutions for Microsoft. As a Senior Front-End CAD Engineer , you'll drive ... SoC and IP design methodologies, partnering with design teams across Microsoft Silicon to deliver... Design compile, elaboration and filelist/libraries handling. - Design release packaging and qualification, RTL quality… more
    Microsoft Corporation (12/03/25)
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  • Physical Design Engineer , 3D…

    Google (Sunnyvale, CA)
    Physical Design Engineer , 3D Technology, PhD, University Graduate _corporate_fare_ Google _place_ Sunnyvale, CA, USA **Mid** Experience driving progress, solving ... and its integration within AI/ML-driven systems. As a Physical Design Engineer in 3D Technology, you will...maturity and tapeout. This will include high impact physical design innovations with through- silicon vias (TSVs) requiring… more
    Google (12/24/25)
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  • Package Design Engineer

    Google (Sunnyvale, CA)
    Package Design Engineer _corporate_fare_ Google _place_ Sunnyvale, CA, USA **Mid** Experience driving progress, solving problems, and mentoring more junior team ... Additionally, you will be instrumental in identifying and incorporating advanced chip packaging technologies into the Google chip product design pipeline. This… more
    Google (12/20/25)
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