• Design Implementation Engineer

    Broadcom (San Jose, CA)
    …+ Hands on experience with timing analysis and place and route tools for ASIC / SoC Design is a must. **Additional Requirements:** + Good problem solver. ... placement, clock tree synthesis, route, timing analysis, timing closure, physical verification (LVS/DRC). + Drive tools and methodologies to achieve desired PPA… more
    Broadcom (12/12/25)
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  • Principal Design Engineer

    Microsoft Corporation (Mountain View, CA)
    …8+ years of experience delivering successful IP or Application Specific Integrated Circuits ( ASIC )/ SOC designs. + 5+ years of experience in Synthesis, Timing ... to help achieve that mission. We are looking for a Principal Design Engineer to work in the dynamic Microsoft Artificial Intelligence System on Chip (AISoC)… more
    Microsoft Corporation (12/14/25)
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  • Silicon Validation Engineer , Reality Labs

    Meta (Sunnyvale, CA)
    …architecture, Intellectual Property, Firmware, Electrical Engineering, System on Chip, and product engineer teams) to generate validation reports for SoC and ... silicon, hardware, software, and content. The Reality Labs team seeks a Silicon Validation Engineer .As a Silicon Validation Engineer , you will be part of the RL… more
    Meta (10/22/25)
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  • Senior Design for Debug Architect and Methodology…

    NVIDIA (Santa Clara, CA)
    …logic analyzers and/or other silicon visibility tools. + Great understanding of ASIC design flow including RTL design, verification , logic synthesis, timing ... a Senior Design for Debug (DFD) Architect and Methodology Engineer ! NVIDIA is seeking a DFD Architect to implement...implement hardware and software solutions to debug world's leading SoC 's and GPU's. This position offers the opportunity to… more
    NVIDIA (12/10/25)
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  • Senior DFT Static Timing Analysis Engineer

    Google (Sunnyvale, CA)
    Senior DFT Static Timing Analysis Engineer , Cloud _corporate_fare_ Google _place_ Sunnyvale, CA, USA **Mid** Experience driving progress, solving problems, and ... static timing (ie, full chip timing signoff ownership, constraint authoring and verification , full chip static timing analysis and timing ECO creation, timing… more
    Google (12/05/25)
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  • Lead C++ Software Engineer

    Cadence Design Systems, Inc. (San Jose, CA)
    …area. + Ideally you are a solid contributor in the FPGA or ASIC prototyping/synthesis/ verification space and have delivered great QoR on these platforms. ... impact on the world of technology. We are looking for an exceptional C++ software engineer to join the Protium Software Development Team to d evelop and enhance the… more
    Cadence Design Systems, Inc. (09/30/25)
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  • Sr. Hardware Engineer - ML Acceleration,…

    Amazon (Cupertino, CA)
    …analysis and trade-offs - Experience with modern ASIC /FPGA design and verification tools - Experience with SOC bring-up and post-silicon validation Amazon ... that help our customers change the world. We are seeking a Hardware Design Engineer with role in the definition, design and validation of AWS next generation ML… more
    Amazon (10/06/25)
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