• DFT Engineer - CPU

    Qualcomm (Santa Clara, CA)
    …+ Experience using the Mentor Tessent tools + Experience with defining and implementing SOC level verification on large designs. + Experience in TCL, Perl/Python ... a smarter, connected future for all. As a DFT Engineer you will work with chip architects, chip designers,...years of practical experience + Strong fundamentals in digital ASIC design; experience using Verilog or VHDL + Experience… more
    Qualcomm (07/04/25)
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  • Processor RTL Design Engineer (Multiple…

    Qualcomm (San Diego, CA)
    …low power Hexagon cores are at the heart of Qualcomm's multi-tier mobile SOC , IoT, Automotive roadmap. The Hexagon architecture is designed to deliver performance ... Machine learning, IoT and Automotive. This position involves in-depth understanding of the ASIC design flow from RTL to GDS2 and the challenges posed by advanced… more
    Qualcomm (07/17/25)
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  • Silicon Validation Engineer , Reality Labs

    Meta (Sunnyvale, CA)
    …architecture, Intellectual Property, Firmware, Electrical Engineering, System on Chip, and product engineer teams) to generate validation reports for SoC and ... silicon, hardware, software, and content. The Reality Labs team seeks a Silicon Validation Engineer .As a Silicon Validation Engineer , you will be part of the RL… more
    Meta (08/01/25)
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  • Lead C++ Software Engineer

    Cadence Design Systems, Inc. (San Jose, CA)
    …area. + Ideally you are a solid contributor in the FPGA or ASIC prototyping/synthesis/ verification space and have delivered great QoR on these platforms. ... impact on the world of technology. We are looking for an exceptional C++ software engineer to join the Protium Software Development Team to d evelop and enhance the… more
    Cadence Design Systems, Inc. (07/01/25)
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  • Senior Design for Debug Architect and Methodology…

    NVIDIA (Santa Clara, CA)
    …logic analyzers and/or other silicon visibility tools. + Great understanding of ASIC design flow including RTL design, verification , logic synthesis, timing ... a Senior Design for Debug (DFD) Architect and Methodology Engineer ! NVIDIA is seeking a DFD Architect to implement...implement hardware and software solutions to debug world's leading SoC 's and GPU's. This position offers the opportunity to… more
    NVIDIA (06/11/25)
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  • Senior FPGA Prototyping Engineer - Hardware

    NVIDIA (Santa Clara, CA)
    …emphasis on Synopsys Protocompiler or Synplify Premier and Xilinx Vivado + Exposure to ASIC design and verification tools (VCS or equivalent, Verdi, GDB). + ... We are now looking for a Senior FPGA Prototyping Engineer to join our Emulation team onsite in Santa...of the design. + Good coordination with architects, designers, verification engineers, and SW teams will be needed to… more
    NVIDIA (06/10/25)
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  • Senior Hardware Modeling Simulation SDE, AWS…

    Amazon (Cupertino, CA)
    …Our team builds functional models of these ML accelerator chips to speed up SoC verification and system software development. We're looking for a Hardware ... Modeling Simulation SDE (Software Development Engineer ) to join the team and deliver new C++...Experience programming with C++ and/or SystemC - Familiarity with SoC , CPU, GPU, and/or ASIC architecture and… more
    Amazon (08/13/25)
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