• Digital Design Engineer

    Meta (Sunnyvale, CA)
    …tests in C for custom hardware 5. Help create and maintain design documentation including IP/ SoC Micro Architecture document (collaborator/owner), IP/ SoC ... with Digital Verification (DV) 3. Support back end physical design (PD) through STA and SDCs 4....practical experience 7. 6+ years of experience in digital design , hardware engineering or related experience 8.… more
    Meta (09/09/25)
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  • Physical Design Flow and Methodology…

    Google (Sunnyvale, CA)
    …an emphasis on computer architecture. + 10 years of experience in physical design flow and methodologies for high-performance ASIC/ SoC projects. + Experience in ... Physical Design Flow and Methodology Engineer _corporate_fare_ Google _place_...(Caliber/IC Validator), Formal Verification (LEC), Extraction, Low Power Verification, STA closure, and ECO flows. + Familiarity with 2.5D/3D… more
    Google (10/24/25)
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  • Sr Principal Product Engineer - Memory IP

    Cadence Design Systems, Inc. (San Jose, CA)
    …more than 30 years of computational software expertise. We apply our Intelligent System Design strategy to deliver software, hardware , and IP that turn design ... and debug of Memory IP subsystems. + Support customer SOC and system integration, including ATE deployment and production...modern life depends on. We are a global electronic design automation company, providing software, hardware , and… more
    Cadence Design Systems, Inc. (11/22/25)
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  • Senior Silicon Bringup and Test Lead, Raxium

    Google (Fremont, CA)
    …qualifications:** + 15 years of experience in Application-Specific Integrated Circuit/System on Chip (ASIC/ SoC ) design , with a focus on both digital logic ... practical experience. + 10 years of experience in analog circuit design , including simulation and verification. + Experience working with relevant Electronic… more
    Google (11/22/25)
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  • Lead Speed and Reliability Engineer - DFP

    NVIDIA (Santa Clara, CA)
    … hardware engineering position. + Previous engineering experience in CPU/GPU/ SOC NPI bringup, with focus on driving methodologies and testplans. Familiarity ... a plus, related to timing, speed, reliability and power. + Familiarity with STA timing closure, circuit design , noise characterization, product binning methods… more
    NVIDIA (11/15/25)
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