• Digital Design Engineer

    Meta (Austin, TX)
    …7+ years of experience as a Digital Design Engineer 9. Experience with top level integration using automation tools. 10. Experience in RTL coding, synthesis ... Digital Design Engineer Responsibilities: 1. Responsible for top - level or block level uArchitecture...and/or SoC Integration. 11. Experience in digital design more
    Meta (05/13/25)
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  • Design Verification Engineer - Machine…

    Meta (Austin, TX)
    …and C/C++ based verification 10. 8+ years of experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM/OVM based methodologies 11. ... 6. Support hand-off and integration of developed subsystems/IP blocks into larger SOC environments 7. Develop and drive continuous Design Verification… more
    Meta (06/24/25)
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  • Design Verification Engineer

    Meta (Austin, TX)
    …verification and UVM methodology 9. 2+ years experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM/OVM based methodologies 10. ... to validate new core IP or System on Chip ( SoC ) implementations. You will work closely with researchers, architects...track detailed test plans for the different modules and top levels 3. Drive Design Verification to… more
    Meta (07/12/25)
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  • ASIC Design Engineer, Cloud-Scale Machine…

    Amazon (Austin, TX)
    …the right trade-offs. Key job responsibilities - integrate multiple subsystems into top level SOC , ensure correct clock/reset/functional/DFT signal routing ... - BS in Electrical Engineering or related technical field - 5+ years in RTL design for SOC - 5+ years in VLSI engineering - 5+ years with code quality tools… more
    Amazon (06/18/25)
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  • Senior Post Silicon Engineer

    Amazon (Austin, TX)
    …job responsibilities * Lead comprehensive validation and characterization planning for MODEM SOC and high-speed peripherals (LPDDR4, SerDes) * Design and develop ... for high-speed interfaces and peripheral (I3C, QSPI, Ethernet) * Conduct system- level debugs in collaboration with cross-functional teams ( Design , DV,… more
    Amazon (06/14/25)
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  • Server Chipset Power Engineer

    Qualcomm (Austin, TX)
    …optimization. + Experience in design and/or analysis of low power features at SoC , chipset and platform level + Experience in hardware and software co- ... team. If you possess a deep understanding of Server SoC designs and have a passion for architecting and...skills and able to work in dynamic environment with top level engineers and technologists **Minimum Qualifications:**… more
    Qualcomm (08/08/25)
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  • ASIC Implementation Engineer - Timing

    Meta (Austin, TX)
    …1. Develop Timing Constraints for RTL-Synthesis and PrimeTime-STA for the blocks and the top - level including SOC . Analyze the inter-block timing and come up ... teams and vendors **Preferred Qualifications:** Preferred Qualifications: 14. Experience with SOC Design Integration & Front End Implementation 15. Experience… more
    Meta (07/20/25)
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  • ASIC Implementation Engineer - Synthesis

    Meta (Austin, TX)
    …7. Develop Timing Constraints for RTL-Synthesis and PrimeTime-STA for the blocks and the top - level including SOC . Analyze the inter-block timing and come up ... teams and vendors **Preferred Qualifications:** Preferred Qualifications: 17. Experience in SOC Design Integration and Front-End Implementation 18. Knowledge of… more
    Meta (07/20/25)
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  • Server Chipset Project Engineer

    Qualcomm (Austin, TX)
    …+ Must have good communication skills and able to work in dynamic environment with top level engineers and technologists . ** Level of Responsibility:** * ... with 15 years of experience in semiconductor product development (Ex: System design , SoC architecture, HW design and validation, Silicon test, SW… more
    Qualcomm (08/08/25)
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  • ASIC Engineer, Formal Verification

    Meta (Austin, TX)
    …used across the group, both at the top level and at the block level 3. Work with Architecture and Design team to come up with formal specification and ... close coverage with targeted Formal Verification Techniques at IP, Subsystem and SoC level 5. Build reusable/scalable environments for Formal Verification and… more
    Meta (08/01/25)
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