• Digital FPGA Engineer Level 4 (AHT)

    Northrop Grumman (Los Angeles, CA)
    …Verilog within the past 3 years. + Experience with AMD/Xilinx and/or Intel/Altera SoC FPGAs + Experience with Electronic Design Automation (EDA) Tools: Vivado, ... Grumman's Defense Systems** is currently seeking a **Digital FPGA Engineer ** **Level 4** with the desire to learn new...The selected individual will work on FPGA and ASIC Design across the full product life cycle process. In… more
    Northrop Grumman (09/07/25)
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  • Silicon Validation Engineer (Mid to Senior…

    ManpowerGroup (Mountain View, CA)
    …C++ for scripting and automation. + Solid understanding of computer architecture and SoC design principles. + Strong analytical and problem-solving skills with ... leader in cutting-edge technology, is seeking a Silicon Validation Engineer (Mid to Senior Level) to join their team....silicon debug tools and automation frameworks. + Collaborate with design , verification , and software teams to identify… more
    ManpowerGroup (09/23/25)
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  • Digital FPGA Engineer Level 3 (AHT)

    Northrop Grumman (Los Angeles, CA)
    …Verilog within the past 3 years. + Experience with AMD/Xilinx and/or Intel/Altera SoC FPGAs + Experience with Electronic Design Automation (EDA) Tools: Vivado, ... Grumman's Defense Systems** is currently seeking a **Digital FPGA Engineer ** **Level 3** with the desire to learn new...The selected individual will work on FPGA and ASIC Design across the full product life cycle process. In… more
    Northrop Grumman (10/02/25)
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  • FPGA Engineer (Starship Electronics)

    SpaceX (Hawthorne, CA)
    …digital designs + Experience in different stages of FPGA development: RTL design , verification , synthesis, timing analysis, lab bring up/validation + Experience ... FPGA Engineer (Starship Electronics) Hawthorne, CA Apply SpaceX was...highly reliable firmware and gateware for SpaceX-designed hardware + Design and implement signal processing algorithms relating to communications… more
    SpaceX (07/15/25)
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  • DFT Engineer

    Broadcom (San Jose, CA)
    …Account, please Sign-In before you apply.** **Job Description:** **Principal DFT Engineer ** Broadcom's ASIC Product Division is seeking candidates for a DFT ... way from chip level DFT specification, through to implementation and verification culminating in successfully releasing products to production. The candidate would… more
    Broadcom (09/05/25)
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  • ASIC Engineer

    ManpowerGroup (Folsom, CA)
    …**Pay Range:** $90/hr - $105/hr **What's the Job?** + Oversee definition, design , verification , and documentation for ASIC development. + Determine architecture ... client, a leading technology firm, is seeking an ASIC Engineer to join their team. As an ASIC ... design , logic design , and system simulation. +… more
    ManpowerGroup (08/15/25)
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  • Senior Systems Prototyping Engineer

    NVIDIA (Santa Clara, CA)
    …on Synopsys Protocompiler or Synplify Premier and Xilinx Vivado + Exposure to ASIC design and verification tools (VCS or equivalent, Verdi, GDB). + Knowledge of ... We are now looking for a Senior Systems Prototyping Engineer to join our Emulation team onsite in Santa...Build FPGA prototypes by making RTL FPGA-friendly, partitioning the design and taking it through synthesis and place and… more
    NVIDIA (09/17/25)
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  • Embedded C++ Software Engineer , Machine…

    Amazon (Cupertino, CA)
    …upon, documented, tested, and reused - Close collaboration with RTL designers, design verification engineers, and other software teams Basic Qualifications - ... Description Are you the type of engineer who thrives at the intersection of hardware...of hardware accelerated neural network models deep within the SOC 's Neuron Cores. You'll also work closely with our… more
    Amazon (08/08/25)
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  • ASIC Engineer , Implementation

    Meta (Sunnyvale, CA)
    …to Job" online on this web page. **Required Skills:** ASIC Engineer , Implementation Responsibilities: 1. Run logic/physical synthesis using advanced optimization ... level and identify power reduction opportunities. 4. Run formal verification checks between RTL & gate level netlist and...domain crossing checks. 9. Understand reset-architecture and work with design & FW teams to develop reset groups and… more
    Meta (09/20/25)
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  • Lead C++ Software Engineer

    Cadence Design Systems, Inc. (San Jose, CA)
    …impact on the world of technology. We are looking for an exceptional C++ software engineer to join the Protium Software Development Team to d evelop and enhance the ... used by leading CPU/GPU/HyperScaler companies for pre-Silicon software validation of their SOC 's. You will develop new algorithms and optimizations for QoR (Quality… more
    Cadence Design Systems, Inc. (09/30/25)
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