• Silicon Architect, Reality Labs

    Meta (San Diego, CA)
    …Work cross-functionally with SoC and IP architecture, performance/power modeling, logic design and verification , physical implementation, firmware, CAD, ... Architect who will collaborate with a world-class group of SoC and IP architects, modeling, development, and validation teams,... design issues 9. Hands-on experience in digital design , logic simulation, and performance analysis **Preferred… more
    Meta (10/20/25)
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  • Senior DV Engineer

    Capgemini (Santa Clara, CA)
    …more areas-Ethernet, Mixed Signal Digital design verification , Formal Property Verification (Jasper or similar tools), or ARM-based SoC verification . ... **About the Job You're Considering** We're seeking a ** Design Verification Engineer** for a **hybrid...subsystem, and SoC . + Collaborate closely with logic designers to debug failures and resolve design… more
    Capgemini (11/14/25)
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  • Senior Reset and Boot ASIC Engineer

    NVIDIA (Santa Clara, CA)
    … synthesis, and timing analysis of several modules. + Integrate modules into the overall SOC design and work closely with other teams in the silicon bring-up ... Science and related (or equivalent experience) + 5+ years of SoC design /integration experience, including architecture and implementation of system-level… more
    NVIDIA (09/30/25)
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  • Sr. FPGA Engineer (Starshield)

    SpaceX (Hawthorne, CA)
    …digital designs + Experience in different stages of FPGA development: RTL design , verification , synthesis, timing analysis, lab bring up/validation + Experience ... As an Sr. FPGA engineer on the satellite digital design team, you will be designing, developing, and testing...integrating logic onto SoC platforms and designing high-throughput… more
    SpaceX (09/30/25)
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  • ASIC Engineer, Implementation

    Meta (Sunnyvale, CA)
    …related occupation. Requires one year of experience in the following: 16. 1. Logic synthesis and design optimization for Power, Performance, and Area 17. ... page. **Required Skills:** ASIC Engineer, Implementation Responsibilities: 1. Run logic /physical synthesis using advanced optimization techniques and generate optimized… more
    Meta (09/20/25)
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  • FPGA Engineer (Starshield)

    SpaceX (Hawthorne, CA)
    …digital designs + Experience in different stages of FPGA development: RTL design , verification , synthesis, timing analysis, lab bring up/validation + Experience ... driven, and collaborative engineers. As an FPGA engineer on the satellite digital design team, you will be designing, developing, and testing FPGAs that supports… more
    SpaceX (09/30/25)
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  • Digital FPGA Engineer Level 3 (AHT)

    Northrop Grumman (Acton, CA)
    …Verilog within the past 3 years. + Experience with AMD/Xilinx and/or Intel/Altera SoC FPGAs + Experience with Electronic Design Automation (EDA) Tools: Vivado, ... The selected individual will work on FPGA and ASIC Design across the full product life cycle process. In...or other STEM discipline with 5 years of digital verification engineering experience using industry standard simulation tools; 3… more
    Northrop Grumman (10/29/25)
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  • Senior Systems Prototyping Engineer

    NVIDIA (Santa Clara, CA)
    …on Synopsys Protocompiler or Synplify Premier and Xilinx Vivado + Exposure to ASIC design and verification tools (VCS or equivalent, Verdi, GDB). + Knowledge of ... be doing: + Build FPGA prototypes by making RTL FPGA-friendly, partitioning the design and taking it through synthesis and place and route. + Improve performance… more
    NVIDIA (09/17/25)
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  • Lead C++ Software Engineer

    Cadence Design Systems, Inc. (San Jose, CA)
    …used by leading CPU/GPU/HyperScaler companies for pre-Silicon software validation of their SOC 's. You will develop new algorithms and optimizations for QoR (Quality ... of super star engineers to develop our next generation FPGA based verification platform. Responsibilities: + Implement new algorithm and enhancements in C/C++ based… more
    Cadence Design Systems, Inc. (09/30/25)
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