- Meta (Sunnyvale, CA)
- …online on this web page. **Required Skills:** ASIC Engineer , Design Verification Responsibilities: 1. Define and implement block/IP/ SoC verification ... plans, build verification test benches to enable block/IP/sub-system/ SoC level verification . 2. Develop functional tests based on verification test plan.… more
- Meta (Sacramento, CA)
- …online on this web page. **Required Skills:** ASIC Engineer , Design Verification Responsibilities: 1. Define and implement IP/ SoC verification plans, ... build verification test benches to enable IP/sub-system/ SoC level verification and develop functional tests based on verification test plan. 2.… more
- Arrow Electronics (Mountain View, CA)
- **Position:** Design Verification Engineer **Job Description:** Principal Accountabilities * Responsible for architecting Verification Environment for ASIC ... SoC and providing verification support from defining verification plan to multi-million gate product tapeout & for Test design and development * Develop… more
- Meta (Sunnyvale, CA)
- …to build IP and System On Chip ( SoC ) for data center applications. As a Formal Verification Engineer , you will be part of a team working with the best in the ... **Summary:** Meta is hiring ASIC Formal Verification Engineer within the Infrastructure organization....create formal environment and close coverage with targeted Formal Verification Techniques at IP, Subsystem and SoC … more
- Meta (Sunnyvale, CA)
- …entire stack, from transistor, through architecture, to firmware, and algorithms. As a Design Verification Engineer at Meta Reality Labs, you will work with an ... of the art IPs or SoCs. **Required Skills:** Design Verification Engineer Responsibilities: 1. Work with researchers...UVM methodology 10. 2+ years experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM/OVM… more
- Meta (Sunnyvale, CA)
- …at the entire stack, through algorithms to architecture, transistors to firmware.As a Design Verification Engineer at Meta's Reality Labs, you will work with a ... multiple state of the art machine learning IPs. **Required Skills:** Design Verification Engineer - Machine Learning Accelerators Responsibilities: 1. Work with… more
- Qualcomm (San Diego, CA)
- …that meet performance, security, technology, and feature requirements. As a Design Verification Engineer , you will work with Chip Architects to validate ... to help create a smarter, connected future for all. As a Qualcomm Design Verification Hardware Engineer , you will plan, design, optimize, verify, and test… more
- Amazon (Sunnyvale, CA)
- …is powering the latest generation of Echo devices is looking for a Senior Design Verification Engineer to continue to innovate on behalf of our customers. We are ... Design Verification of Subsystems such as CPU, NPU, and SOC . Drive Verification Methodology using System Verilog / C++ based test benches. Basic… more
- Qualcomm (Santa Clara, CA)
- …Engineering Group, Engineering Group > CPU Engineering **General Summary:** As a Design Verification Engineer , you will work with Chip Architects to validate the ... concepts of CPU and SOC level micro-architectures. You will work on a selected...work on a selected part of the CPU Design Verification to ensure that it functions to the standards… more
- Amazon (Sunnyvale, CA)
- …is powering the latest generation of Echo devices is looking for a Senior Design Verification Engineer to continue to innovate on behalf of our customers. We are ... Design Verification of Subsystems such as CPU, NPU, and SOC . - Drive Verification Methodology using System Verilog / C++ based test benches. Basic… more